7.3.9 VPWR Undervoltage and UVLO Events

This section lists the behavior of VPWR undervoltage and UVLO events when the voltage at the VDD pin is uninterrupted.

When the voltage at the VPWR pin falls below V_{PUV_F} the following occurs.

• The VPUV bit in the Supply Event Register is set.
• All ports are shut off.
• For ports that are shut off the corresponding PGCn and PECn bits in the Power Event Register is set and the PGn and PEn bits in the Power Status Register are cleared.
• The following registers are cleared.
  • Detection Event Register
  • Fault Event Register
  • Start/ILIM Event Register
  • Port n Status Register
  • Detect/Class Enable Register

NOTE

When the voltage at the VPWR pin falls below V_{UVLOPW_F} the following occurs.

• Both the VPUV and VDUV bits in the Supply Event Register is set
• All ports are shut off
• All registers are set to their power-on/reset state