ZHCSNB6A April   2021  – February 2022 TPS23882B

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1. 6.1 Detailed Pin Description
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Timing Diagrams
  9. 9 Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Operating Modes
        1. 9.1.1.1 Auto
        2. 9.1.1.2 Autonomous
        3. 9.1.1.3 Semiauto
        4. 9.1.1.4 Manual and Diagnostic
        5. 9.1.1.5 Power Off
      2. 9.1.2 PoE Compliance Terminology
      3. 9.1.3 PoE 2 Type-3 2-Pair PoE
      4. 9.1.4 Requested Class Versus Assigned Class
      5. 9.1.5 Power Allocation and Power Demotion
      6. 9.1.6 Programmable SRAM
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Port Remapping
      2. 9.3.2 Port Power Priority
      3. 9.3.3 Analog-to-Digital Converters (ADC)
      4. 9.3.4 I2C Watchdog
      5. 9.3.5 Current Foldback Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Detection
      2. 9.4.2 Classification
      3. 9.4.3 DC Disconnect
    5. 9.5 I2C Programming
      1. 9.5.1 I2C Serial Interface
    6. 9.6 Register Maps
      1. 9.6.1 Complete Register Set
      2. 9.6.2 Detailed Register Descriptions
        1. 9.6.2.1  INTERRUPT Register
        2. 9.6.2.2  INTERRUPT MASK Register
        3. 9.6.2.3  POWER EVENT Register
        4. 9.6.2.4  DETECTION EVENT Register
        5. 9.6.2.5  FAULT EVENT Register
        6. 9.6.2.6  START/ILIM EVENT Register
        7. 9.6.2.7  SUPPLY and FAULT EVENT Register
          1. 9.6.2.7.1 Detected SRAM Faults and "Safe Mode"
        8. 9.6.2.8  CHANNEL 1 DISCOVERY Register
        9. 9.6.2.9  CHANNEL 2 DISCOVERY Register
        10. 9.6.2.10 CHANNEL 3 DISCOVERY Register
        11. 9.6.2.11 CHANNEL 4 DISCOVERY Register
        12. 9.6.2.12 POWER STATUS Register
        13. 9.6.2.13 PIN STATUS Register
          1. 9.6.2.13.1 AUTONOMOUS MODE
        14. 9.6.2.14 OPERATING MODE Register
        15. 9.6.2.15 DISCONNECT ENABLE Register
        16. 9.6.2.16 DETECT/CLASS ENABLE Register
        17. 9.6.2.17 Power Priority / 2Pair PCUT Disable Register Name
        18. 9.6.2.18 TIMING CONFIGURATION Register
        19. 9.6.2.19 GENERAL MASK Register
        20. 9.6.2.20 DETECT/CLASS RESTART Register
        21. 9.6.2.21 POWER ENABLE Register
        22. 9.6.2.22 RESET Register
        23. 9.6.2.23 ID Register
        24. 9.6.2.24 Connection Check and Auto Class Status Register
        25. 9.6.2.25 2-Pair Police Ch-1 Configuration Register
        26. 9.6.2.26 2-Pair Police Ch-2 Configuration Register
        27. 9.6.2.27 2-Pair Police Ch-3 Configuration Register
        28. 9.6.2.28 2-Pair Police Ch-4 Configuration Register
        29. 9.6.2.29 Capacitance (Legacy PD) Detection
        30. 9.6.2.30 Power-on Fault Register
        31. 9.6.2.31 PORT RE-MAPPING Register
        32. 9.6.2.32 Channels 1 and 2 Multi Bit Priority Register
        33. 9.6.2.33 Channels 3 and 4 Multi Bit Priority Register
        34. 9.6.2.34 Port Power Allocation Register
        35. 9.6.2.35 TEMPERATURE Register
        36. 9.6.2.36 INPUT VOLTAGE Register
        37. 9.6.2.37 CHANNEL 1 CURRENT Register
        38. 9.6.2.38 CHANNEL 2 CURRENT Register
        39. 9.6.2.39 CHANNEL 3 CURRENT Register
        40. 9.6.2.40 CHANNEL 4 CURRENT Register
        41. 9.6.2.41 CHANNEL 1 VOLTAGE Register
        42. 9.6.2.42 CHANNEL 2 VOLTAGE Register
        43. 9.6.2.43 CHANNEL 3 VOLTAGE Register
        44. 9.6.2.44 CHANNEL 4 VOLTAGE Register
        45. 9.6.2.45 2x FOLDBACK SELECTION Register
        46.       93
        47. 9.6.2.46 FIRMWARE REVISION Register
        48. 9.6.2.47 I2C WATCHDOG Register
        49. 9.6.2.48 DEVICE ID Register
        50. 9.6.2.49 CHANNEL 1 DETECT RESISTANCE Register
        51. 9.6.2.50 CHANNEL 2 DETECT RESISTANCE Register
        52. 9.6.2.51 CHANNEL 3 DETECT RESISTANCE Register
        53. 9.6.2.52 CHANNEL 4 DETECT RESISTANCE Register
        54. 9.6.2.53 CHANNEL 1 DETECT CAPACITANCE Register
        55. 9.6.2.54 CHANNEL 2 DETECT CAPACITANCE Register
        56. 9.6.2.55 CHANNEL 3 DETECT CAPACITANCE Register
        57. 9.6.2.56 CHANNEL 4 DETECT CAPACITANCE Register
        58. 9.6.2.57 CHANNEL 1 ASSIGNED CLASS Register
        59. 9.6.2.58 CHANNEL 2 ASSIGNED CLASS Register
        60. 9.6.2.59 CHANNEL 3 ASSIGNED CLASS Register
        61. 9.6.2.60 CHANNEL 4 ASSIGNED CLASS Register
        62. 9.6.2.61 AUTO CLASS CONTROL Register
        63. 9.6.2.62 CHANNEL 1 AUTO CLASS POWER Register
        64. 9.6.2.63 CHANNEL 2 AUTO CLASS POWER Register
        65. 9.6.2.64 CHANNEL 3 AUTO CLASS POWER Register
        66. 9.6.2.65 CHANNEL 4 AUTO CLASS POWER Register
        67. 9.6.2.66 ALTERNATIVE FOLDBACK Register
        68. 9.6.2.67 SRAM CONTROL Register
          1. 9.6.2.67.1 SRAM START ADDRESS (LSB) Register
          2. 9.6.2.67.2 SRAM START ADDRESS (MSB) Register
          3. 9.6.2.67.3 118
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Autonomous Operation
      2. 10.1.2 Introduction to PoE
        1. 10.1.2.1 2-Pair Versus 4-Pair Power and the New IEEE802.3bt Standard
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Connections on Unused Channels
        2. 10.2.2.2 Power Pin Bypass Capacitors
        3. 10.2.2.3 Per Port Components
        4. 10.2.2.4 System Level Components (not Shown in the Schematic Diagrams)
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 VDD
    2. 11.2 VPWR
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Kelvin Current Sensing Resistors
      2.      138
    2. 12.2 Layout Example
      1. 12.2.1 Component Placement and Routing Guidelines
        1. 12.2.1.1 Power Pin Bypass Capacitors
        2. 12.2.1.2 Per-Port Components
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 接收文档更新通知
    3. 13.3 支持资源
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 术语表
  14. 14Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

9.6.2.19 GENERAL MASK Register

COMMAND = 17h with 1 Data Byte, Read/Write

Figure 9-24 GENERAL MASK Register Format
76543210
INTEN–nbitACCMbitPrtyCLCHEDECHE– –
R/W-1R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-24 GENERAL MASK Register Field Descriptions
BitFieldTypeResetDescription
7INTENR/W1INT pin mask bit. Writing a 0 will mask any bit of Interrupt register from activating the INT output, whatever the state of the Interrupt Mask register. Note that activating INTEN has no impact on the event registers.

1 = Any unmasked bit of Interrupt register can activate the INT output

0 = INT output cannot be activated

6–R/W0
5nbitACCR/W0I2C Register Access Configuration bit.

1 = Configuration B. This means 16-bit access with a single device address (A0 = 0).

0 = Configuration A. This means 8-bit access, while the 8-channel device is treated as 2 separate 4-channel devices with 2 consecutive target addresses.

See register 0x11 for more information on the I2C address programming

4MbitPrtyR/W0Multi Bit Priority bit. Used to select between 1-bit shutdown priority and 3-bit shutdown priority.

1 = 3-bit shutdown priority. Register 0x27 and 0x28 need to be followed for priority and OSS action.

0 = 1-bit shutdown priority. Register 0x15 needs to be followed for priority and OSS action

3CLCHER/W0Class change Enable bit. When set, the CLSCn bits in Detection Event register only indicates when the result of the most current classification operation differs from the result of the previous one.

1 = CLSCn bit is set only when a change of class occurred for the associated channel.

0 = CLSCn bit is set each time a classification cycle occurred for the associated channel.

2DECHER/W0Detect Change Enable bit. When set, the DETCn bits in Detection Event register only indicates when the result of the most current detection operation differs from the result of the previous one.

1 = DETCn bit is set only when a change in detection occurred for the associated channel.

0 = DETCn bit is set each time a detection cycle occurred for the associated channel.

1–R/W0
0–R/W0

Note:

If the MbitPrty bit needs to be changed from 0 to 1, make sure the OSS input pin is in the idle (low) state for a minimum of 200 µsec prior to setting the MbitPrty bit, to avoid any misbehavior related to loss of synchronization with the OSS bit stream.

Note:

Only the nbitACC bit for channels 1-4 needs to be set to enable 16-bit I2C operation.

Table 9-25 nbitACC = 1: Register Operations in 8-Bit (Config A) and 16-bit (Config B) I2C Mode
Cmd CodeRegister or Command NameBits DescriptionConfiguration A (8-bit)Configuration B (16-bit)
00hINTERRUPTINT bits P1-4, P5-8Separate mask and interrupt result per group of 4 channels.
The Supply event bit is repeated twice.
01hINTERRUPT MASKMSK bits P1-4, P5-8
02hPOWER EVENTPGC_PEC P4-1, P8-5Separate event byte per group of 4 channels.
03h
04hDETECTION EVENTCLS_DET P4-1, P8-5
05h
06hFAULT EVENTDIS_PCUT P4-1, P8-5
07h
08hSTART/ILIM EVENTILIM_STR P4-1, P8-5
09h
0AhSUPPLY/FAULT EVENTTSD, VDUV, VDUW, VPUV , RAMFLT OSSE4-1, OSSE8-5Both 8-bit registers (channel 1 to 4 and channel 5 to 8) will show the same results for TSD, VDUV, VPUV and RAMFLT. The PCUTxx and OSSEx bits will. have separate status per group of 4 channels.
Clearing at least one VPUV/VDUV also clears the other one.
0Bh
0ChCHANNEL 1 DISCOVERYCLS&DET1_CLS&DET5Separate Status byte per channel
0DhCHANNEL 2 DISCOVERYCLS&DET2_CLS&DET6
0EhCHANNEL 3 DISCOVERYCLS&DET3_CLS&DET7
0FhCHANNEL 4 DISCOVERYCLS&DET4_CLS&DET8
10hPOWER STATUSPG_PE P4-1, P8-5Separate status byte per group of 4 channels
11hPIN STATUSA4-A1,A0Both 8-bit registers (channel 1 to 4 and channel 5 to 8) will show the same result, except that A0 = 0 (channel 1 to 4) or 1 (channel 5 to 8).Both 8-bit registers (channel 1 to 4 and channel 5 to 8) will show the same result, including A0 = 0.
12hOPERATING MODEMODE P4-1, P8-5Separate Mode byte per group of 4 channels.
13hDISCONNECT ENABLEDCDE P4-1, P8-5Separate DC disconnect enable byte per group of 4 channels.
14hDETECT/CLASS ENABLECLE_DETE P4-1, P8-5Separate Detect/Class Enable byte per group of 4 channels.
15hPWRPR/2P-PCUT DISABLEOSS_DCUT P4-1, P8-5Separate OSS/DCUT byte per group of 4 channels.
16hTIMING CONFIGTLIM_TSTRT_TOVLD_TMPDO P4-1,
P8-5		Separate Timing byte per group of 4 channels.
17hGENERAL MASKP4-1, P8-5 including n-bit accessSeparate byte per group of 4 channels.
n-bit access: Setting this in at least one of the virtual quad register space is enough to enter Config B mode. To go back to config A, clear both.
MbitPrty: Setting this in at least one of the virtual quad register space is enough to enter 3-bit shutdown priority. To go back to 1-bit shutdown, clear both MbitPrty bits.
18hDETECT/CLASS RestartRCL_RDET P4-1, P8-5Separate DET/CL RST byte per group of 4 channels
19hPOWER ENABLEPOF_PWON P4-1, P8-5Separate POF/PWON byte per group of 4 channels
1AhRESETP4-1, P8-5Separate byte per group of 4 channels, Clear Int pin and Clear All int.
Separate byte per group of 4 channels.
1BhIDBoth 8-bit registers (channel 1 to 4 and channel 5 to 8) will show the same result unless modified through I2C.
1ChAUTOCLASSAC4-1, AC8-5Separate byte per group of 4 channels.
1Eh2P POLICE 1/5 CONFIGPOL1, POL5Separate Policing byte per channel.
1Fh2P POLICE 2/6 CONFIGPOL2, POL6
20h2P POLICE 3/7 CONFIGPOL3, POL7
21h2P POLICE 4/8 CONFIGPOL4, POL8
22hCAP MEASUREMENTCDET4-1, CDET8-5Separate capacitance measurement enable bytes per group of 4 channels.
24hPower-on FAULTPF P4-1, P8-5Separate Power-on FAULT byte per group of 4 channels
25h
26hPORT REMAPPINGLogical P4-1, P8-5Separate Remapping byte per group of 4 channels.
Reinitialized only if POR or RESET pin. Kept unchanged if 0x1A IC reset or CPU watchdog reset.
27hMulti-Bit Priority 21 / 65MBP2-1, MBP6-5Separate MBP byte per group of 2 channels
28hMulti-Bit Priority 43 / 87MBP4-3, MBP8-7Separate MBP byte per group of 2 channels
29hPORT POWER ALLOCATION MC34-12, MC78-56Separate MCnn byte per group of 4 channels
2ChTEMPERATURETEMP P1-4, P5-8Both 8-bit registers (channel 1 to 4 and channel 5 to 8) must show the same result.
2EhINPUT VOLTAGEVPWR P1-4, P5-8Both 8-bit registers (channel 1 to 4 and channel 5 to 8) must show the same result.
2Fh
30hCHANNEL 1 CURRENTI1, I5Separate 2-byte per group of 4 channelsSeparate 2-byte per group of 4 channels.
2-byte Read at 0x30 gives I1
4-byte Read at 0x30 gives I1, I5.
31hN/A2-byte Read at 0x31 gives I5.
32hCHANNEL 1 VOLTAGEV1, V5Separate 2-byte per group of 4 channels2-byte Read at 0x32 gives V1
4-byte Read at 0x32 gives V1, V5.
33hN/A2-byte Read at 0x33 gives V5.
34hCHANNEL 2 CURRENTI2, I6Separate 2-byte per group of 4 channels2-byte Read at 0x34 gives I2
4-byte Read at 0x34 gives I2, I6.
35hN/A2-byte Read at 0x35 gives I6.
36hCHANNEL 2 VOLTAGEV2, V6Separate 2-byte per group of 4 channels2-byte Read at 0x36 gives V2
4-byte Read at 0x36 gives V2, V6.
37hN/A2-byte Read at 0x37 gives V6.
38hCHANNEL 3 CURRENTI3, I7Separate 2-byte per group of 4 channels2-byte Read at 0x38 gives I3
4-byte Read at 0x38 gives I3, I7.
39hN/A2-byte Read at 0x39 gives I7.
3AhCHANNEL 3 VOLTAGEV3, V7Separate 2-byte per group of 4 channels2-byte Read at 0x3A gives V3
4-byte Read at 0x3A gives V3, V7.
3BhN/A2-byte Read at 0x3B gives V7.
3ChCHANNEL 4 CURRENTI4, I8Separate 2-byte per group of 4 channels2-byte Read at 0x3C gives I4
4-byte Read at 0x3C gives I4, I8.
3DhN/A2-byte Read at 0x3D gives I8.
3EhCHANNEL 4 VOLTAGEV4, V8Separate 2-byte per group of 4 channels2-byte Read at 0x3E gives V4
4-byte Read at 0x3E gives V4, V8.
3FhN/A2-byte Read at 0x3F gives V8.
40hOPERATIONAL FOLDBACK2xFB4-1, 2xFB8-5Separate 2xFBn config byte per group of 4 channels.
41hFIRMWARE REVISIONFRV P1-4, P5-8Both 8-bit registers (channel 1 to 4 and channel 5 to 8) must show the same result.
42hI2C WATCHDOGP1-4, P5-8IWD3-0: if at least one of the two 4-port settings is different than 1011b, the watchdog is enabled for all 8 channels.
WDS: Both 8-bit registers (channel 1 to 4 and channel 5 to 8) must show the same WDS result. Each WDS bit needs to be cleared individually through I2C.
43hDEVICE IDDID_SR P1-4, P5-8Both 8-bit registers (channel 1 to 4 and channel 5 to 8) will show the same result .
44hCHANNEL 1 RESISTANCERDET1, RDET5Separate byte per channel.
Detection resistance always updated, detection good or bad.
45hCHANNEL 2 RESISTANCERDET2, RDET6
46hCHANNEL 3 RESISTANCERDET3, RDET7
47hCHANNEL 4 RESISTANCERDET4, RDET8
4ChCHANNEL 1 ASSIGNED CLASSACLS&PCLS1_ACLS&PCLS5Separate Status byte per channel
4DhCHANNEL 2 ASSIGNED CLASSACLS&PCLS2_ACLS&PCLS6
4EhCHANNEL 3 ASSIGNED CLASSACLS&PCLS3_ACLS&PCLS7
4FhCHANNEL 4 ASSIGNED CLASSACLS&PCLS4_ACLS&PCLS8
50hAUTOCLASS CONTROLMAC4-1, AAC4-1, MAC8-5, AAC8-5Separate Auto Class control bytes per 4 channels
51hAUTOCLASS POWER 1/5PAC1, PAC5Separate Auto Class Power Measurement byte per channel
52hAUTOCLASS POWER 2/6PAC2, PAC6
53hAUTOCLASS POWER 3/7PAC3, PAC7
54hAUTOCLASS POWER 4/8PAC4, PAC8
55hALTERNATIVE FOLDBACKALTFB4-1, ALTIR4-1, ALTFN8-5, ALTIR8-5Separate Alternative Foldback byte per group of 4 channels
60hSRAM CONTROLSRAM CNTRL BITSThese bits must be configured for the lower virtual quad (A0=0, CH 1-4)). These bits have no functionality for the upper virtual quad (A0=1, Ch 5-8) device
61hSRAM DATAStreaming data input is independent of I2C configuration
62hSTART ADDRESS (LSB)These bits must be configured for the lower virtual quad (A0=0, CH 1-4)). These bits have no functionality for the upper virtual quad (A0=1, Ch 5-8) device
63hSTART ADDRESS (MSB)These bits must be configured for the lower virtual quad (A0=0, CH 1-4)). These bits have no functionality for the upper virtual quad (A0=1, Ch 5-8) device
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