An I²C Watchdog timer is available on the TPS23882B device. The timer monitors the I²C, SCL line for clock edges. When enabled, a timeout of the watchdog resets the I²C interface along with any active ports. This feature provides protection in the event of a hung software situation or I²C bus hang-up by target devices. In the latter case, if a target is attempting to send a data bit of 0 when the controller stops sending clocks, then the target may drive the data line low indefinitely. Because the data line is driven low, the controller cannot send a STOP to clean up the bus. Activating the I²C watchdog feature of the TPS23882B clears this deadlocked condition. If the timer of two seconds expires, the ports latch off and the WD status bit is set. Note that WD Status is set even if the watchdog is not enabled. The WD status bit can only be cleared by a device reset or writing a 0 to the WDS status bit location. The 4-bit watchdog disable field shuts down this feature when a code of 1011b is loaded. This field is preset to 1011b whenever the TPS23882B is initially powered. See I²C WATCHDOG Register for more details.