4 修订历史记录

Changes from F Revision (February 2015) to G Revision

• Changed the values of the Power limit threshold in Electrical Characteristics for V_OUT = 7 V and V_OUT = 2 V From: 10, 12.5, 15 mV To: 10.1, 11.6, 13.1 mVGo
• Changed the title of Figure 8 From: MOSFET Gate Current vs Voltage Across R_SENSE During Inrush Power Limiting To: Gate Current vs Voltage Across R_SENSEGo
• Added Figure 9 Go
• Changed V_{(VCC–SENSE)} To: V_{(SENSE–VCC)} in Figure 10 and Figure 11Go
• Added Equation 1 Go
• Added text to the PROG section: "To compute the Power limit based on an existing R_PROG..." Go
• Changed Equation 2 Go
• Changed text in STEP 3. Choose Power-Limit Value, PLIM, and RPROG From: "a 53.6-kΩ, 1% resistor is selected for R_PROG" To: a 44.2-kΩ, 1% resistor is selected for R_PROG"Go
• Changed Equation 9 Go
• Added the Using Soft Start with TPS2471x section Go

Changes from E Revision (November 2013) to F Revision

• 已添加 ESD 额定值表，特性 描述 部分，器件功能模式，应用和实施部分，电源相关建议部分，布局部分，器件和文档支持部分以及机械、封装和可订购信息部分.Go
• Changed the Input voltage range, PROG - MAX value in the Absolute Maximum Ratings table From: 0.3 To: 3.6 Go
• Deleted External capacitance - GATE from the Recommended Operating ConditionsGo
• Deleted text from the last paragraph in the GATE section "If used, any capacitor connecting GATE and GND should not exceed 1 μF and it should be connected in series with a resistor of no less than 1 kΩ."Go
• Deleted section: Alternative Design Example: GATE Capacitor (dV/dt) Control in Inrush ModeGo
• Deleted text from the High-Gate-Capacitance Applications section "When gate capacitor dV/dt control is used, ... then a Zener diode is not necessary."Go

Changes from D Revision (November 2013) to E Revision

• Reverted Equation 2 in rev E back to rev CGo
• Reverted Equation 9 in rev E back to rev CGo

Changes from C Revision (May 2011) to D Revision

• Added Note 1 to the Supply Current Conditions statementGo
• Added Note 1 to Fast-turnoff delay Go
• Changed the Functional Block Diagram From: V_CC = 6 V to V_CC = 5.9 V at the Gate ComparatorGo
• Changed text in the GATE section From: "Timer Activation Voltage (6 V for V_VCC = 12 V)." To: "Timer Activation Voltage (5.9 V for V_VCC = 12 V)."Go
• Changed the first paragraph of the Inrush Operation sectionGo
• Added text and new Equation 10Go
• Changed text prior to Equation 12 From: "6 V (for V_VCC = 12 V)" To: "5.9 V (for V_VCC = 12 V)"Go
• Changed the text following Equation 12Go
• Changed text following Alternative Design Example: GATE Capacitor (dV/dt) Control in Inrush Mode From: "Set P_LIM to a value greater than V_VCC × I_CHG" To: "Choose I_CHG < P_LIM / V_VCC"Go
• Changed Equation 15 From: – C_ISS To: – C_RS (this equation deleted by Revision F)Go

Changes from B Revision (April 2011) to C Revision

• Changed in PGb: from: 140V/340mV, to:170mV / 240mV Go
• Changed in Equation 8: r_DS(on) to R_SENSEGo

Changes from A Revision (March 2011) to B Revision

• Corrected voltage values shown in Figure 26Go