Table 2. Design Requirements for 30A ORing then Hot Swap

10.2.3.1 Select R_SNS and V_SNS,CL Setting

TPS2474x has a programmable V_SNS,CL with a recommended range of 10 mV to 67.5 mV. It can be used with a V_SNS,CL up to 200 mV, but that requires a resistor (R_STBL) between SET and SENM to ensure stability of an internal loop. R_STBL should be set larger than R_IMON x R_SET / (10xR_SET- R_IMON). This is shown in Figure 31.

For the majority of applications 25mV (R_STBL is not needed) is a good starting target for V_SNS,CL. Targeting a current limit of 35A to allow margin for the load, the sense resistor can be calculated as follows

Equation 10.

Since 0.71 mΩ resistors aren’t available, the closest standard resistor should be chosen. To have better efficiency, a 0.5 mΩ resistor is chosen. Next the V_SNS,CL should be computed based on the actual R_SNS and then used to compute R_SET and R_IMON. R_SET is chosen to target 250 µA of current through SET and IMON pins during current limit.

Equation 11.

Equation 12.

Choose R_SET to equal 69.8Ω, which is the closest available standard resistor. Next obtain the calculated R_IMON (R_IMON,CLC) as follows:

Equation 13.

Choose 2.67kΩ resistor for R_IMON, which is the closest available standard resistor. Since precision current monitoring is desired, 0.1% resistors were used for R_IMON and for R_SET and a 4 terminal sense resistor (WSL4026L5000) was used for R_SNS.

Equation 14.

Equation 15.

Figure 31. Adding R_STBL for V_SNS,CL > 67.5mV

10.2.3.2 Selecting the Fast Trip Threshold and Filtering

The TPS2474x allows the user to program the fast trip threshold. When this threshold is exceeded the gate is quickly pulled down. C_FSTP can be added to include some filtering into the comparator. The selection of the fast trip threshold and filtering is influenced by the systems environment and requirements. In general picking a larger threshold and larger filtering time will result in more immunity to nuisance trips, but also a slower response (possibly inadequate) to real fault conditions. It’s best to fine tune these threshold after testing the real system. As a starting point it is recommended to set the fast trip threshold at least 1.25x larger than then current limit. For this design example a 50A fast trip threshold along with a 500ns filtering time constant were targeted. The value for R_FSTP and C_FSTP can be computed as shown below:

Equation 16.

Equation 17.

The next closest standard resistor and capacitor values should be chosen. In this case R_FSTP = 249Ω and C_FSTP=2nF.

10.2.3.3 Selecting the Hot Swap FET(s)

It is critical to select the correct MOSFET for a Hot Swap design. The device must meet the following requirements:

• The V_DS rating should be sufficient to handle the maximum system voltage along with any ringing caused by transients. For most 12V systems a 25 V or 30V FET is a good choice.
• The SOA of the FET should be sufficient to handle all usage cases: start-up, hot-short, start into short.
• R_DSON should be sufficiently low to maintain the junction and case temperature below the maximum rating of the FET. In fact, it is recommended to keep the steady state FET temperature below 125°C to allow margin to handle transients.
• Maximum continuous current rating should be above the maximum load current and the pulsed drain current must be greater than the current threshold of the circuit breaker. Most MOSFETs that pass the first three requirements will also pass these two.
• A V_GS rating of +16 V is required, because the TPS2474x can pull up the gate as high as 15.5 V above source.

For this design the CSD16415Q was selected for its low R_DSON and superior SOA. After selecting the MOSFET, the maximum steady state case temperature can be computed as follows:

Equation 18.

Note that the R_DSON is a strong function of junction temperature, which for most MOSFETS will be very close to the case temperature. A few iterations of the above equations may be necessary to converge on the final R_DSON and T_C,MAX value. According to the CSD16415Q datasheet, its R_DSON is about 1.3x greater at 100°C compared to room temperature. The equation below uses this R_DSON value to compute the T_C,MAX. Note that the computed T_C,MAX is close to the junction temperature assumed for R_DSON. Thus no further iterations are necessary.

Equation 19.

10.2.3.4 Select Power Limit

In general, a lower power limit setting is preferred to reduce the stress on the MOSFET. However, at low power limit levels both the V_SNS and V_IMON become very low, which results in more error caused by offsets. It is recommended to keep V_SNS above 1.5mV and V_IMON above 27mV to ensure reasonable accuracy of the power limit engine. Based on these requirements the minimum power limit can be computed as seen in Equation 20.

Equation 20.

In most applications the power limit can be set to P_LIM,MIN using Equation 21. Here R_SNS and R_PWR are in Ωs and P_LIM is in Watts.

Equation 21.

The closest available resistor should be selected. In this case it is a 113 kΩ.

10.2.3.5 Set Fault Timer

The inrush timer runs when the Hot Swap is in power limit or current limit, which is the case during start-up. Thus the timer has to be sized large enough to prevent a time-out during start-up. If the part starts directly into current limit (I_LIM × V_IN < P_LIM) the maximum start time can be computed with Equation 22:

Equation 22.

For most designs (including this example) I_LIM × V_IN > P_LIM so the Hot Swap will start in power limit and transition into current limit. In that case the maximum start time can be computed as seen in Equation 23:

Equation 23.

Note that the above start-time is based on typical current limit and power limit values. To ensure that the timer never times out during start-up it is recommended to set the fault time (TINR) to be 1.5x t_start,max or 4.9 ms. This will account for the variation in power limit, timer current, and timer capacitance.

Next the design should decide if having equal TINR and TFLT is acceptable. If there is no transient load requirement this is usually fine. For this example the same capacitor is connected to both TINR and TFLT to save on BOM cost. In this case the time out (T_TMR) should be set based on the TINR requirements. When these pins are connected the C_TMR can be computed as follows:

The next largest available C_TMR is chosen as 33nF. Once the C_TMR is chosen the actual programmed time out can be computed as seen in Equation 25.

Equation 25.

10.2.3.6 Check MOSFET SOA

Once the power limit and fault timer are chosen, it is critical to check that the FET remains within its SOA during all test conditions. For this design example the TPS24740 is used, which retries once during a hot-short.

During a “Hot-Short” the circuit breaker trips and the TPS24740 re-starts into power limit until the timer runs out. In the worst case the MOSFET’s V_DS will equal V_IN,MAX, I_DS will equal P_LIM / V_IN,MAX and the stress event will last for T_TMR. For this design example the MOSFET will have 13 V, 3 A across it for 5.6 ms.

Based on the SOA of the CSD16415Q, it can handle 13 V, 100 A for 1 ms and it can handle 13 V, 15 A for 10 ms. The SOA for 5.6 ms can be extrapolated by approximating SOA vs time as a power function as shown in Equation 26:

Equation 26.

Note that the SOA of a MOSFET is specified at a case temperature of 25°C, while the case temperature can be much hotter during a hot-short. The SOA should be de-rated based on T_C,MAX using Equation 27:

Equation 27.

Based on this calculation the MOSFET can handle 11.67 A, 13 V for 5.6 ms at elevated case temperature, but is only required to handle 3A (39 W / 13 V) during a hot-short. Thus there is good margin and this will be a robust design. In general, it is recommended that the MOSFET can handle 1.3x more than what is required during a hot-short. This provides margin to cover the variance of the power limit and fault time.

10.2.3.7 Choose ORing MOSFET

When selecting the ORing MOSFET the considerations are similar to the Hot Swap MOSFET, but the SOA is no longer critical. In addition the lower R_DSON is not always ideal, because that would result in a larger reverse current for the same reverse voltage threshold. Of course a lower R_DSON would provide better efficiency. For consistency sake a single CSD16415Q FET was used for the ORing section as well. It is important to check its steady state temperature at max load using the same equation that was used for the Hot Swap.

Equation 28.

10.2.3.8 Choose Reverse Current Threshold and Filtering

When setting the reverse current threshold, it is often desired to set a very low value to minimize the maximum DC reverse current. However, the accuracy of the reverse voltage threshold should be considered. The TPS2474x has a 1mV offset on the reverse voltage comparator. Thus setting a very low reverse voltage setting can result in some boards to trip at positive current. This would lead to oscillations at zero load condition as the ORing gate turns ON and OFF, which is typically not desired. Note that applications that always have a significant forward current will not experience this problem.

For this design example a reverse voltage of 1.5mV was targeted to keep the threshold low, but to also ensure that the device never trips at positive current. Just like the filtering on the fast trip threshold for the Hot Swap, the optimum time constant for filtering the reverse voltage threshold will depend on the system environment and requirements. Again, this is a trade-off between avoiding nuisance trips and a fast response to actual faults. In general a 500ns time constant is a good starting point. Based on these target thresholds, R_RV and C_RV can be computed using Equation 29 and Equation 30.

Equation 29.

Equation 30.

Choose closest available standards values: R_RV = 15Ω and C_RV = 33nF.

10.2.3.9 Choose Under Voltage and Over Voltage Settings

The TPS2474x has comparators with 1.35V threshold on the ENHS, ENOR, and OV pins. A resistor divider can be used to set Undervoltage and Overvoltage thresholds for the bus. For this design example 10V and 14V were chosen as the limits to allow some margin for the 11V to 13V input bus. Once these limits are known, R_DIV2 and R_DIV3 can be computed using Equation 31, Equation 32, and Equation 33. R_DIV1 was set to 49.9 kΩ, which keeps the power consumption reasonably low without being too susceptible to leakage currents.

Equation 31.

Equation 32.

Equation 33.

Choose closest available standard 1% resistors: R_DIV2 = 2.21 kΩ and R_DIV3 = 5.62 kΩ. The actual Under Voltage and Over Voltage settings can be computed for the chosen resistors as shown in Equation 34 and Equation 35:

Equation 34.

Equation 35.

10.2.3.10 Selecting C_IN, C_OUT, and C_MIDDLE

It is recommended to add ceramic bypass capacitors to help stabilize the voltages on the input, output, and the intermediate node. Since C_IN and C_MIDDLE will be charged directly on hot-plug, their value should be kept small. 0.1µF is a good target. Since C_OUT doesn’t get charged during hot-plug, a larger value such as 1 µF could be used.

10.2.3.11 Selecting D1 and D2

During hot plug and hot short events there could be significant transients on the input and output of the hotswap that could cause operation outside of the IC specifications. To ensure reliable operation a TVS on the input and a Schottky diode on the output are recommended. In this example a SMDJ14A and MBRS330T3G are used.

10.2.3.12 Ensuring Stability

For most applications, the TPS2474x is stable whithout any additional components. However in some cases additional C_GS,EXT is required as shown in Figure 32 to help stabilize the current and power limit loop. Typically this is for low current limits and low sense voltages. It is easy to check whether these extra components are needed using the equations below. Note that the transconductance ( also referred to as g_m and g_fs) of the FET will vary based on the current and thus g_m' is used in the equations as a normalizing parameter. The CSD16415 has a gm of 168 siemens at 40A of I_DS, resulting in g_m' of 26.56. For this example, C_GS,MIN was computed to be 0.9nF, while the C_ISS of the CSD16415 is 3.15nF providing plenty of margin for the design. In general it is recommended to have a 2x margin from the typical C_ISS and C_GS,MIN to account for any variation that the FET would have. If the C_ISS of the MOSFET isn't large enough an external RC should be added as shown in the figure below. Note that if parallel FETs are used C_GS,MIN (per FET) is reduced by square root of two or by 1.41.

Equation 36.

Equation 37.

Equation 38.

Figure 32. Ensuring Stability

10.2.3.13 Compute Tolerances

After finishing a design it is often desired to know the variations of each setting. Often times there are multiple error sources and there are two common ways to analyze the circuit. One is worst case, which adds all of the error sources. The other one is root mean square (RMS), which is less conservative. When error sources are independent using the RMS method provides a more statistically accurate view of the tolerances. This method is used in this section. Note that the error calculations are quite long and tedious and it is recommended to use TI’s excel tools, which support both worst case and RMS analysis. For this example the tolerances in Table 3 are assumed. See Tools & Software link on the Product folder.

First, the tolerance of the current monitoring and current limit is computed.

There are 5 error sourcing contributing to the current monitoring accuracy on the IMON pin: tolerance of R_SET (ER_SET), tolerance of R_IMON (ER_IMON), tolerance of R_SNS (ER_SNS), the IC gain error (ER_GAIN), and the IC offset error (ER_OS). All of these errors are in % with the exception of the offset error. To get a percent error due to the offset error (ER_OS%) simply divide the offset by the sense voltage. For the TPS2474x, ER_GAIN is 0.4%, and ER_OS is 150 µV.

Based on these values the full scale (I_FS,ERR,IMON) and 20% of full scale (I_{20FS,ERR,IMON}) current monitoring accuracy at the Imon pin can be computed with Equation 39 and Equation 40.

Equation 39.

Equation 40.

Note that the TPS24740 detects the current limit when the IMON pin exceeds 675 mV. Thus the current limit error I_LIM,ER is a combination of the I_FS,ERR,IMON and the current limit error at the IMON pin (I_LIM,ERR,IMON). The 675 mV threshold varies up to 15 mV so I_LIM,ERR,IMON is 2.3% and the current limit error can be computed as seen in Equation 41:

Equation 41.

If the current is monitored at the IMONBUF pin, there is additional error introduced due to the internal buffer, which has a gain error of 0.66% (ER_OS,BUF) and an offset error of 3mV (ER_OS,BUF) referred to the IMON pin. Note that V_IMON equals 675 mV at full scale and 135 mV at 20% of full scale. Thus the total current monitoring error at the IMONBUF pin for full scale (I_{FS,ERR,IMONBUF}) and 20% of full scale (I_{20FS,ERR,IMONBUF}) can be found using Equation 42 and Equation 43 :

Equation 42.

Equation 43.

Next the power limit error is computed. This error is made up of three sources: the error from external components (ERR_COMP), the error when translating the sense voltage to IMON (I_PL,ERR,IMON), and the error of the power limit engine at IMON (ERR_IMON,PL). Both ERR_SNS and ERR_{IMON, PL} are a function of the operating point of the power limit engine. Note that this error is greatest at largest V_DS, since V_SNS,PL is smallest (refer to Figure 20). For this example V_DS is largest when V_IN = 13 V (maximum V_IN) and V_OUT = 0 V and thus the error is computed at this operating point. The sense voltage (V_SNS) and the voltage at the IMON pin (V_IMON) should be computed for this operating point using Equation 44 and Equation 45:

Equation 44.

Equation 45.

The I_PL,ERR,IMON can be computed similarly to I_FS,ERR,IMON using Equation 46.

Equation 46.

The tolerance of the power limit engine is specified at three V_IMON points in the datasheet: 135 mV (±20.3 mV), 67.5 mV (±10.1 mV), and 27 mV (±8.1 mV). To get the % error at the real operating point, the absolute error should be extrapolated and divided by V_IMON as shown in Equation 47. This is graphically depicted in Figure 33.

Equation 47.

Figure 33. Extrapolating Power Limit Error

Once ERR_IMON,PL and I_PL,ERR,IMON are known the total power limit error (PL_ERR,TOT) can be computed using Equation 48. The component error comes from R_SNS (1%), R_PLIM (1%), R_SET (0.1%), and R_IMON (0.1%) resulting in a total component error of 1.4%.

Equation 48.

After computing the fast trip voltage threshold to be 24.9 mV (100 µA × 249 Ω), the fast trip threshold error resulting from the IC (FST_{ERR, IC}) can be computed using a similar extrapolation method as used for power limit. The component error of R_SNS and R_FST should be added to obtain the total fast trip error (FST_ERR,TOT) showin in Equation 49 and Equation 50 below.

Equation 49.

Equation 50.

The IC error of the UV/OV threshold is always 3.7% (0.05 V/1.35 V). Assuming that all resistors have a 1% error the component error is 1.41% (2 resistors). When using the RMS method the total error is 4%. For the timer error, the IC contributes 22% and 10% comes from the component. When using the RMS method the total error becomes 24.1%.

Table 4 summarizes the final tolerances of the design:

10.2.5.1 Design Requirements

This second design example is similar to the first one, but has a few key differences. First of all, the maximum output capacitance is much larger, and the maximum current is also larger, which puts more stress on the MOSFET. On the flip side, the TPS24742 IC is used, which results in less MOSFET stress during a hot-short event, because there is no restart. Finally, there is a requirement that the design should allow for 60A to pass through for 200 ms without shutting down. This requires the use of two timers. In addition, there is no requirement for accurate current monitoring and hence it’s not necessary to use a 4 terminal sense resistor.

10.2.5.2 Design Procedure

10.2.5.2.1 Select R_SNS and V_SNS,CL Setting

Similarly to the previous design example, 25mV is used as a starting target for V_SNS,CL. Targeting a current limit of 45A to allow margin for the load, the sense resistor can be computed as follows:

Equation 51.

Since 0.55 mΩ resistors aren’t available, the closest standard resistor should be chosen. To have better efficiency, a 0.5 mΩ resistor is chosen. Next the V_SNS,CL should be computed based on the actual R_SNS and then used to compute R_SET and R_IMON. R_SET is chosen to target 250 µA of current through SET and IMON pins during current limit.

Equation 52. V_SNS,CL = I_LIM × V_SNS,CL = 45 A × 0.5 mΩ = 22.5 mV

Equation 53. R_SET,CLC = V_SNS,CL/250 µA = 90 Ω

Chose R_SET to equal 90.9Ω, which is the closest available standard resistor. Next obtain the calculated R_IMON (R_IMON,CLC) as follows:

Equation 54.

Choose 2.74kΩ resistor for R_IMON, which is the closest available standard resistor. Since precision current monitoring is not needed 1% resistors were used for R_IMON and for R_SET and a 2 terminal sense resistor (HCS2512FTL500) was used for R_SNS.

Finally, compute the actual current limit (I_LIM,CL) :

Equation 55.

10.2.5.2.2 Selecting the Fast Trip Threshold and Filtering

The TPS2474x allows the user to program the fast trip threshold. When this threshold is exceeded the gate is quickly pulled down. C_FSTP can be added to include some filtering into the comparator. The selection of the fast trip threshold and filtering is influenced by the systems environment and requirements. In general picking a larger threshold and larger filtering time will result in more immunity to nuisance trips, but also a slower response (possibly inadequate) to real fault conditions. It’s best to fine tune these threshold after testing the real system. As a starting point it is recommended to set the fast trip threshold at least 1.25x larger than then current limit. For this design example a 65A fast trip threshold along with a 500ns filtering time constant were targeted to make sure that the 60A load transient can be passed. The value for R_FSTP and C_FSTP can be computed as shown in Equation 56 and Equation 57:

Equation 56.

Equation 57.

The next closest standard resistor and capacitor values should be chosen. In this case R_FSTP = 324Ω and C_FSTP=1.5nF.

10.2.5.2.3 Selecting the Hot Swap FET

It is critical to select the correct MOSFET for a Hot Swap design. The device must meet the following requirements:

• The V_DS rating should be sufficient to handle the maximum system voltage along with any ringing caused by transients. For most 12V systems a 25 V or 30V FET is a good choice.
• The SOA of the FET should be sufficient to handle all usage cases: start-up, hot-short, start into short.
• R_DSON should be sufficiently low to maintain the junction and case temperature below the maximum rating of the FET. In fact, it is recommended to keep the steady state FET temperature below 125°C to allow margin to handle transients.
• Maximum continuous current rating should be above the maximum load current and the pulsed drain current must be greater than the current threshold of the circuit breaker. Most MOSFETs that pass the first three requirements will also pass these two.
• A V_GS rating of +16 V is required, because the TPS2474x can pull up the gate as high as 15.5 V above source.

For this design the CSD16415Q was selected for its low R_DSON and superior SOA. After selecting the MOSFET, the maximum steady state case temperature can be computed as seen in Equation 58:

Equation 58.

Note that the R_DSON is a strong function of junction temperature, which for most MOSFETS will be very close to the case temperature. A few iterations of the above equations may be necessary to converge on the final R_DSON and T_C,MAX value. According to the CSD16415Q datasheet, its R_DSON is about 1.4 × greater at 120°C compared to room temperature. Equation 59 uses this R_DSON value to compute the T_C,MAX. Note that the computed T_C,MAX is close to the junction temperature assumed for R_DSON. Thus no further iterations are necessary.

Equation 59.

10.2.5.2.4 Select Power Limit

In general, a lower power limit setting is preferred to reduce the stress on the MOSFET. However, at low power limit levels both the V_SNS and V_IMON become very low, which results in more error caused by offsets. It is recommended to keep V_SNS above 1.5mV and V_IMON above 27mV to ensure reasonable accuracy of the power limit engine. Based on these requirements the minimum power limit can be computed as shown in Equation 60:

Equation 60.

In most applications the power limit can be set to P_LIM,MIN using the equation below. Here R_SNS and R_PWR are in Ωs and P_LIM is in Watts.

Equation 61.

The closest available resistor should be selected. In this case it is a 143 kΩ.

10.2.5.2.5 Set Fault Timer

The inrush timer runs when the Hot Swap is in power limit or current limit, which is the case during start-up. Thus the timer has to be sized large enough to prevent a time-out during start-up. If the part starts directly into current limit (I_LIM × V_IN < P_LIM) the maximum start time can be computed with Equation 62:

Equation 62.

For most designs (including this example) I_LIM × V_IN > P_LIM so the Hot Swap will start in power limit and transition into current limit. In that case the maximum start time can be computed as seen in Equation 63:

Equation 63.

Note that the above start time is based on typical current limit and power limit values. To ensure that the timer never times out during start-up it is recommended to set the fault time (TINR) to be 1.5x t_start,max or 32.6 ms. This will account for the variation in power limit, timer current, and timer capacitance.

Next the designer should decide if having equal TINR and TFLT is acceptable. Note that to pass the load transient the fault timer needs to be longer than 200 ms. If the inrush time is this long, it will place too much stress on the MOSFET during a start into short. For this reason, it’s ideal to have two separate timers. To ensure proper start up and to pass the load transient a target inrush time (T_INR,TGT) of 32.6 ms and a target fault time (T_FLT,TGT) of 250ms is used. C_INR,CLC and C_FLT,CLC is computed as seen in Equation 64 and Equation 65 :

Equation 64.

Equation 65.

The next largest available C_INR is chosen as 330nF and the next largest available C_FLT is chosen as 2.2µF

Next, the actual T_INR and T_FLT can be computed as shown below: Once C_TMR and C_FLT is chosen the actual programmed time out can be computed as shown in Equation 66 and Equation 67.

Equation 66.

Equation 67.

10.2.5.2.6 Check MOSFET SOA

Once the power limit and fault timer are chosen, it’s critical to check that the FET will stay within its SOA during all test conditions. For this design example the TPS24742 is used, which does not retry during a hot-short. Thus the worst condition is a start-up with output shorted to GND. In this case the TPS24742 will start into a power limit and regulate at that point for 43.5 ms (T_INR). Based on the SOA of the CSD16415Q, it can handle 13 V, 15 A for 10 ms and it can handle 13 V, 4 A for 100 ms. The SOA for 43.5 ms can be extrapolated by approximating SOA vs time as a power function as shown in Equation 68:

Equation 68.

Note that the SOA of a MOSFET is specified at a case temperature of 25°C, while the case temperature can be hotter during a start into a short. It is important to understand the hottest temperature that a MOSFET can be during a start-up (T_{C, MAX, START}). If a board has been off for a while and then it’s turned on T_{A, MAX} is a good estimate for T_{C,MAX, START}. However, if a board is on and then gets power cycled T_C,MAX should be used for T_C,MAX,START. This will depend on system requirements. For this design example it is assumed that the board can only be plugged in cold and T_A,MAX is used to estimate T_C,MAX,START.

Equation 69.

Based on this calculation the MOSFET can handle 4.98 A, 13 V for 43.5 ms at 55°C elevated case temperature, but is only required to handle 3A during a hot-short. Thus there is good margin and this will be a robust design. In general, it is recommended that the MOSFET can handle 1.3x more than what is required during a worst case operating condition. This provides margin to cover the variance of the power limit and fault time.

10.2.5.2.8 Choose ORing MOSFET

When selecting the ORing MOSFET, the considerations are similar to the Hot Swap MOSFET, but the SOA is no longer critical. In addition the lower R_DSON is not always ideal, because that would result in a larger reverse current for the same reverse voltage threshold. Of course a lower R_DSON would provide better efficiency. For consistency sake a single CSD16415Q FET was used for the ORing section as well. It’s important to check its steady state temperature at max load using the same equation that was used for the Hot Swap.

Equation 70.

10.2.5.3 Application Curves

Figure 46. Start up (C_OUT=440µF)

Figure 47. Start up (C_OUT=10,000µF, V_IN = 13V)

Figure 48. Start up Into Short on V_OUT

Figure 50. Hot – Short on V_OUT(zoomed in)

Figure 52. Short Vin (I_LOAD = 10A)

Figure 54. 60A Load Step for 200 ms

Figure 56. Gradual Overcurrent

Figure 49. Hot Short on V_OUT

Figure 51. Under/Over Voltage with V_IN Rising

Figure 53. Gradual Reverse Current

Figure 55. Load Step 40A to 60A