7.4.3 Action of the Constant Power Engine (Figure 14)

The calculated power dissipated in Q1, V_DS ×I_D, is computed under the same startup conditions as Figure 13 . The current of Q1, labeled I_IN, initially rises to the value that satisfies the constant power engine; in this case it is
34 W ÷ 48 V = 0.7 A. The 34 W value is programmed into the engine by setting the PROG voltage using Equation 2 given in the PROG. V_DS of Q1, which is calculated as V_{(SENSE–OUT)}, falls as C_O charges, thus allowing the Q1 drain current to increase. This is the result of the internal constant power engine adjusting the current limit reference to the GATE amplifier as C_O charges and V_DS falls. The calculated device power in Figure 14, labeled FET PWR, is seen to be flat-topped and constant within the limitations of circuit tolerance and acquisition noise. A fixed current limit is implemented by clamping the constant power engine’s output to 50 mV when V_DS is low. This protection technique can be viewed as a specialized form of foldback limiting; the benefit over linear foldback is that it yields the maximum output current from a device over the full range of V_DS and still protects the device.

Figure 14. Computation of Q1 Stress During Startup