11.1 Layout Guidelines

• For the trace routing of DP_IN, DM_IN, DP_OUT, and DM_OUT: Route these traces as micro-strips with nominal differential impedance of 90 Ω. Minimize the use of vias in the high-speed data lines. Keep the reference GND plane devoid from cuts or splits above the differential pairs to prevent impedance discontinuities. For more information, see the High Speed USB Platform Design Guideline from Intel.
• The trace routing from the upstream regulator to the TPS2549 IN pin should as short as possible to reduce the voltage drop and parasitic inductance.
• The traces routing from the R_{ILIM_HI} and R_{ILIM_LO} resistors to the device should be as short as possible to reduce parasitic effects on the current-limit accuracy.
• The thermal pad should be directly connected to the PCB ground plane using a wide and short copper trace.
• The trace routing from the CS pin to the feedback divider of the upstream regulator should not be routed near any noise sources that can capacitively couple to the feedback divider.

11.2 Layout Example

Figure 58. TPS2549 Layout Diagram