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ZHCSFL0 September 2016 TPS2549

PRODUCTION DATA.

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6 Specifications

6.1 Absolute Maximum Ratings

Voltages are with respect to GND unless otherwise noted⁽¹⁾

			MIN	MAX	UNIT
	Voltage range	CS, CTL1, CTL2, CTL3, EN, FAULT, ILIM_HI, ILIM_LO, IN, OUT, STATUS	–0.3	7	V
		DM_IN, DM_OUT, DP_IN, DP_OUT	–0.3	5.7	V
		IN to OUT	–7	7	V
	Continuous current in SDP, CDP or client mode	DP_IN to DP_OUT or DM_IN to DM_OUT	–100	100	mA
	Continuous current in BC1.2 DCP mode	DP_IN to DM_IN	–35	35	mA
	Continuous output current	OUT	Internally limited		A
I_(SRC)	Continuous output source current	ILIM_HI, ILIM_LO	Internally limited		A
I_(SNK)	Continuous output sink current	FAULT, STATUS		25	mA
I_(SNK)	Continuous output sink current	CS	Internally limited		A
T_J	Operating junction temperature		–40	Internally limited	°C
T_stg	Storage temperature		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾		±2,000	V
		Charged-device model (CDM),per JEDEC specification JESD22-C101⁽²⁾		±750
		IEC⁽³⁾	IEC61000-4-2 contact discharge, DP_IN and DM_IN	±8,000
		IEC⁽³⁾	IEC61000-4-2 air discharge, DP_IN and DM_IN	±15,000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

(3) Surges per IEC61000-4-2, 1999 applied between DP_IN/DM_IN and output ground of the TPS2549Q1EVM-729 (SLVUAK6) evaluation module.

6.3 Recommended Operating Conditions

Voltages are with respect to GND unless otherwise noted.

			MIN	MAX	UNIT
V_(IN)	Supply voltage	IN	4.5	6.5	V
	Input voltage	CTL1, CTL2, CTL3, EN	0	6.5	V
	Input voltage	DM_IN, DM_OUT, DP_IN, DP_OUT	0	3.6	V
I_(OUT)	Output continuous current	OUT (–40°C ≤ T_A ≤ 85°C)		3	A
	Continuous current in SDP, CDP or client mode	DP_IN to DP_OUT or DM_IN to DM_OUT	–30	30	mA
	Continuous current in BC1.2 DCP mode	DP_IN to DM_IN	–15	15	mA
	Continuous output sink current	FAULT, STATUS		10	mA
R_{(ILIM_xx)}	Current limit-set resistors		15.4	1000	kΩ
T_J	Operating junction temperature		–40	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS2549	UNIT
		RTE (WQFN)
		16 PINS
R_θJA	Junction-to-ambient thermal resistance	44.9	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	53.3	°C/W
R_θJB	Junction-to-board thermal resistance	17.6	°C/W
ψ_JT	Junction-to-top characterization parameter	1	°C/W
ψ_JB	Junction-to-board characterization parameter	17.6	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	4.1	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

Unless otherwise noted, –40°C ≤ T_J ≤ 125°C and 4.5 V ≤ V_(IN) ≤ 6.5 V, V_(EN) = V_(IN), V_(CTL1)= V_(CTL2) = V_(CTL3) = V_(IN). R_(FAULT) = R_(STATUS) = 10 kΩ, R_{(ILIM_HI)} = 19.1 kΩ, R_{(ILIM_LO)} = 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C. All voltages are with respect to GND.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
OUT – POWER SWITCH
r_DS(on)	On-resistance⁽¹⁾	T_J = 25°C		47	57	mΩ
		–40°C ≤ T_J ≤ 85°C		47	72
		–40°C ≤T_J ≤ 125°C		47	80
I_lkg(OUT)	Reverse leakage current on OUT pin	V_OUT = 6.5 V, V_IN = V_EN = 0 V, –40°C ≤ T_J ≤ 85°C, measure I_(OUT)			2	µA
OUT - DISCHARGE
R_(DCHG)	OUT discharge resistance		400	500	630	Ω
EN, CTL1, CTL2, CTL3 INPUTS
	Input pin rising logic threshold voltage		1	1.35	2	V
	Input pin falling logic threshold voltage		0.85	1.15	1.65	V
	Hysteresis⁽²⁾			200		mV
	Input current	Pin voltage = 0 V or 6.5 V	–1		1	µA
CURRENT LIMIT
I_OS	OUT short-circuit current limit	R_{(ILIM_LO)} = 210 kΩ	205	255	305	mA
		R_{(ILIM_LO)} = 80.6 kΩ	600	660	720
		R_{(ILIM_LO)} = 23.2 kΩ	2145	2300	2455
		R_{(ILIM_HI)} = 20 kΩ	2500	2670	2840
		R_{(ILIM_HI)} = 19.1 kΩ	2620	2800	2975
		R_{(ILIM_HI)} = 15.4 kΩ	3255	3470	3685
		R_{(ILIM_HI)} shorted to GND	5500	7000	8000
SUPPLY CURRENT
I_{(IN_OFF)}	Disabled IN supply current	V_(EN) = 0 V, V_(OUT) = 0 V, –40°C ≤ T_J ≤ 85°C		0.1	5	µA
I_{(IN_ON)}	Enabled IN supply current	V_(CTL)1 = V_(CTL2) = V_(CTL3) = V_(IN)		220	300	µA
		V_(CTL1) = V_(CTL2) = 0 V, V_(CTL3) = V_(IN)		226	300
		V_(CTL2) = V_(IN), V_(CTL1) = V_(CTL3) = 0 V		150	220
		V_(CTL1) = V_(IN), V_(CTL2) = V_(CTL3) = 0 V		115	190
UNDERVOLTAGE LOCKOUT, IN
V_(UVLO)	IN rising UVLO threshold voltage		3.9	4.1	4.3	V
	Hysteresis⁽³⁾	T_J = 25°C		100		mV
FAULT
	Output low voltage	I_(FAULT) = 1 mA			100	mV
	Off-state leakage	V_(FAULT) = 6.5 V			2	µA
STATUS
	Output low voltage	I_(STATUS) = 1 mA			100	mV
	Off-state leakage	V_(STATUS) = 6.5 V			2	µA
THERMAL SHUTDOWN
T_(OTSD2)	Thermal shutdown threshold		155			°C
T_(OTSD1)	Thermal shutdown threshold in current-limit		135			°C
	Hysteresis⁽³⁾			20		°C
LOAD DETECT (V_CTL1 = V_CTL2 = V_CTL3 = V_IN)
I_(LD)	I_OUT load detection threshold	R_{(ILIM_LO)} = 80.6 kΩ, rising load current	630	700	770	mA
	Hysteresis⁽³⁾			50		mA
DP_IN AND DM_IN SHORT-TO-V_BUS PROTECTION
V_(OV)	Overvoltage protection trip threshold	DP_IN and DM_IN rising	3.7	3.9	4.15	V
	Hysteresis⁽³⁾			100		mV
R_{(DCHG_Data)}	Discharge resistance after OVP	V_{(DP_IN)} = V_{(DM_IN)} = 5 V	160	210	240	kΩ
CABLE COMPENSATION
I_(CS)	Sink current	Load = 3 A, 2.5 V ≤ V_(CS) ≤ 6.5 V	214	225	236	µA
		Load = 2.4 A, 2.5 V ≤ V_(CS) ≤ 6.5 V	171	180	189
		Load = 2.1 A, 2.5 V ≤ V_(CS) ≤ 6.5 V	149	158	166
		Load = 1 A, 2.5 V ≤ V_(CS) ≤ 6.5 V	70	75	80
HIGH-BANDWIDTH ANALOG SWITCH
R_{(HS_ON)}	DP and DM switch on-resistance	V_{(DP_OUT)} = V_{(DM_OUT)} = 0 V, I_{(DP_IN)} = I_{(DM_IN)} = 30 mA		2	4	Ω
R_{(HS_ON)}	DP and DM switch on-resistance	V_{(DP_OUT)} = V_{(DM_OUT)} = 2.4 V, I_{(DP_IN)} = I_{(DM_IN)} = –15 mA		2.9	6	Ω
\|ΔR_{(HS_ON)}\|	Switch resistance mismatch between DP and DM channels	V_{(DP_OUT)} = V_{(DM_OUT)} = 0 V, I_{(DP_IN)} = I_{(DM_IN)} = 30 mA		0.05	0.15	Ω
\|ΔR_{(HS_ON)}\|	Switch resistance mismatch between DP and DM channels	V_{(DP_OUT)} = V_{(DM_OUT)} = 2.4 V, I_{(DP_IN)} = I_{(DM_IN)} = –15 mA		0.05	0.15	Ω
C_{(IO_OFF)}	DP/DM switch off-state capacitance⁽⁴⁾	V_EN = 0 V, V_{(DP_IN)} = V_{(DM_IN)} = 0.3 V, Vac = 0.03 V_PP , f = 1 MHz		6.7		pF
C_{(IO_ON)}	DP/DM switch on-state capacitance⁽⁴⁾	V_{(DP_IN)} = V_{(DM_IN)} = 0.3 V, Vac = 0.03 V_PP, f = 1 MHz		10		pF
	Off-state isolation⁽⁴⁾	V_EN = 0 V, f = 250 MHz		27		dB
	On-state cross-channel isolation⁽⁴⁾	f = 250 MHz		23		dB
I_lkg(OFF)	Off-state leakage current, DP_OUT and DM_OUT	V_EN = 0 V, V_{(DP_IN)} = V _{(DM_IN)} = 3.6 V, V_{(DP_OUT)} = V_{(DM_OUT)} = 0 V		0.1	1.5	µA
BW	Bandwidth (–3 dB)⁽⁴⁾	R_(L) = 50 Ω		925		MHz
CHARGING DOWNSTREAM PORT DETECT
V_{(DM_SRC)}	DM_IN CDP output voltage	V_{(DP_IN)} = 0.6 V, –250 µA < I_{(DM_IN)} < 0 µA	0.5	0.6	0.7	V
V_{(DAT_REF)}	DP_IN rising lower window threshold for V_{DM_SRC} activation		0.36		0.4	V
	Hysteresis⁽⁴⁾			50		mV
V_{(LGC_SRC)}	DP_IN rising upper window threshold for VDM_SRC de-activation		0.8		0.88	V
V_{(LGC_SRC_HYS)}	Hysteresis⁽⁴⁾			100		mV
I_{(DP_SINK)}	DP_IN sink current	V_{(DP_IN)} = 0.6 V	40	75	100	µA
BC1.2 DCP MODE
R_{(DPM_SHORT)}	DP_IN and DM_IN shorting resistance			125	200	Ω
DIVIDER3 MODE
V_{(DP_DIV3)}	DP_IN output voltage		2.57	2.7	2.84	V
V_{(DM_DIV3)}	DM_IN output voltage		2.57	2.7	2.84	V
R_{(DP_DIV3)}	DP_IN output impedance	I_{(DP_IN)} = –5 µA	24	30	36	kΩ
R_{(DM_DIV3)}	DM_IN output impedance	I_{(DM_IN)} = –5 µA	24	30	36	kΩ
1.2-V MODE
V_{(DP_1.2V)}	DP_IN output voltage		1.12	1.2	1.26	V
V_{(DM_1.2V)}	DM_IN output voltage		1.12	1.2	1.26	V
R_{(DP_1.2V)}	DP_IN output impedance	I_{(DP_IN)} = –5 µA	84	100	126	kΩ
R_{(DM_1.2V)}	DM_IN output impedance	I_{(DM_IN} = –5 µA	84	100	126	kΩ

(1) Pulse-testing techniques maintain junction temperature close to ambient temperature. Thermal effects must be taken into account separately.

(2) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's product warranty.

(3) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's product warranty.

(4) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's product warranty.

6.6 Switching Characteristics

Unless otherwise noted –40°C ≤ T_J ≤ 125°C and 4.5 V ≤ V_(IN) ≤ 6.5 V, V_(EN) = V_(IN), V_(CTL1) = V_(CTL2) = V_(CTL3) = V_(IN). R_(FAULT) = R(_STATUS) = 10 kΩ, R_{(ILIM_HI)} = 19.1 kΩ, R_{(ILIM_LO)} = 80.6 kΩ. Positive current is into pins. Typical value is at 25°C. All voltages are with respect to GND.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_r	OUT voltage rise time	V_(IN) = 5 V, C_(L) = 1 µF, R_(L) = 100 Ω (see Figure 32 and Figure 33)	0.7	1.14	2	ms
t_f	OUT voltage fall time		0.2	0.35	0.6	ms
t_on	OUT voltage turnon time	V_(IN) = 5 V, C_(L) = 1 µF, R_(L) = 100 Ω (see Figure 32 andFigure 35)		4.15	6	ms
t_off	OUT voltage turnoff time			1.8	3	ms
t_{(DCHG_L)}	Long OUT discharge hold time (SDP, CDP, or client mode to DCP_Auto)	Time V_(OUT) < 0.7 V (see Figure 34)	1.1	2	2.9	s
t_{(DCHG_S)}	Short OUT discharge hold time (DCP_Auto to SDP, CDP, or client mode)	Time V_(OUT) < 0.7 V (see Figure 34)	186	320	450	ms
t_(IOS)	OUT short-circuit response time⁽¹⁾	V_(IN) = 5 V, R_(SHORT) = 50 mΩ (see Figure 25)		2		µs
t_{(OC_OUT_FAULT)}	OUT FAULT deglitch time	Bidirectional deglitch applicable to current limit condition only (no deglitch assertion for OTSD)	5.5	8	11.5	ms
t_pd	Analog switch propagation delay ⁽¹⁾	V_(IN) = 5 V		0.14		ns
t_(SK)	Analog switch skew between opposite transitions of the same port (t_PHL – t_PLH) ⁽¹⁾	V_(IN) = 5 V		0.02		ns
t_{(LD_SET)}	Load-detect set time	V_(IN) = 5 V (See Figure 27)	120	210	280	ms
t_{(LD_RESET)}	Load-detect reset time	V_(IN) = 5 V (See Figure 28)	1.8	3	4.2	s
t_{(OV_D)}	DP_IN and DM_IN over-voltage protection response time	V_(OUT) = 5 V (See Figure 29)		2		µs
t_{(OV_D_FAULT)}	DP_IN and DM_IN FAULT degltich time	V_(OUT) = 5 V (See Figure 30)	11	16	23	ms

(1) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's product warranty.

6.7 Typical Characteristics

V_IN = 5 V

Figure 1. Power Switch On-Resistance vs Temperature

V_IN = 5 V

Figure 2. Reverse Leakage Current vs Temperature

Figure 3. OUT Discharge Resistance vs Temperature

CTL1 = 1

CTL2 = 1

CTL3 = 1

Figure 5. Disabled IN Supply Current vs Temperature

CTL1 = 0

CTL2 = 0

CTL3 = 1

Figure 7. Enabled IN Supply Current – DCP_Auto (001) vs Temperature

CTL1 = 1

CTL2 = 0

CTL3 = 0

Figure 9. Enabled IN Supply Current – Client Mode (100) vs Temperature

V_IN = 5 V

Figure 11. DP_IN Overvoltage Protection Threshold vs Temperature

V_IN = 5 V

V_CS = 2. 5 V

Figure 13. I_CS vs Temperature

Figure 15. Data Transmission Characteristics vs Frequency

Figure 17. On-State Cross-Channel Isolation vs Frequency

V_IN = 5 V

Figure 4. OUT Short-Circuit Current Limit vs Temperature

CTL1 = 1

CTL2 = 1

CTL3 = 1

Figure 6. Enabled IN Supply Current – CDP (111) vs Temperature

CTL1 = 0

CTL2 = 1

CTL3 = 0

Figure 8. Enabled IN Supply Current – SDP (010) vs Temperature

R_{(ILIM_LO)} = 80.6 kΩ

Figure 10. I_OUT Rising Load-Detect Threshold and OUT Short-Circuit Current Limit vs Temperature

V_IN = 5 V

Figure 12. DM_IN Overvoltage Protection Threshold vs Temperature

V_IN = 6.5 V

Figure 14. I_CS vs V_CS Voltage

Figure 16. Off-State Data-Switch Isolation vs Frequency

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Figure 18. Eye Diagram Using USB Compliance Test Pattern, Bypassing the TPS2549 Data Switch

R_(LOAD) = 5 Ω

C_(LOAD) = 150 µF

t = 1 ms/div

Figure 20. Turnon Response

R_{(ILIM_HI)} = 80.6 kΩ

t = 2 ms/div

Figure 22. Enable Into Short

R_{(ILIM_HI)} = 19.1 kΩ

t = 4 ms/div

Figure 24. Short-Circuit to Full-Load Recovery

R_{(ILIM_HI)} = 19.1 kΩ

R_(SHORT) = 50 mΩ

t = 1 ms/div

Figure 26. Hot Short

R_{(ILIM_LO)} = 80.6 kΩ

t = 1 s/div

Figure 28. Load Detection Reset Time

R_{(DM_OUT)} = 15 kΩ

t = 4 ms/div

Figure 30. DM_IN Short to V_BUS

Figure 19. Eye Diagram Using USB Compliance Test Pattern, Through the TPS2549 Data Switch

R_(LOAD) = 5 Ω

C_(LOAD) = 150 µF

t = 1 ms/div

Figure 21. Turnoff Response

R_{(ILIM_HI)} = 19.1 kΩ

t = 4 ms/div

Figure 23. Enable Into Short – Thermal Cycling

R_(SHORT) = 50 mΩ

t = 1 µs/div

Figure 25. Hot-Short Response Time

R_{(ILIM_LO)} = 80.6 kΩ

t = 100 ms/div

Figure 27. Load-Detection Set Time

R_{(DM_OUT)} = 15 kΩ

t = 1 µs/div

Figure 29. DM_IN Short to V_BUS Response Time

R_{(DM_OUT)} = 15 kΩ

t = 1 µs/div

Figure 31. DM_IN Short-to-V_BUS Recovery

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6 Specifications

6.1 Absolute Maximum Ratings

6.2 ESD Ratings

6.3 Recommended Operating Conditions

6.4 Thermal Information

6.5 Electrical Characteristics

6.6 Switching Characteristics

6.7 Typical Characteristics