ZHCSGV1C June   2017  – March 2018 TPS25740B

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 VBUS Capacitance
      2. 8.1.2 USB Data Communications
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  ENSRC
      2. 8.3.2  USB Type-C CC Logic (CC1, CC2)
      3. 8.3.3  USB PD BMC Transmission (CC1, CC2, VTX)
      4. 8.3.4  USB PD BMC Reception (CC1, CC2)
      5. 8.3.5  Discharging (DSCG, VPWR)
        1. 8.3.5.1 Discharging after a Fault (VPWR)
      6. 8.3.6  Configuring Voltage Capabilities (HIPWR)
      7. 8.3.7  Configuring Power Capabilities (PSEL, PCTRL, HIPWR)
      8. 8.3.8  Gate Driver (GDNG, GDNS)
      9. 8.3.9  Fault Monitoring and Protection
        1. 8.3.9.1 Over/Under Voltage (VBUS)
        2. 8.3.9.2 Over-Current Protection (ISNS, VBUS)
        3. 8.3.9.3 System Fault Input (GD, VPWR)
      10. 8.3.10 Voltage Control (CTL1, CTL2,CTL3)
      11. 8.3.11 Sink Attachment Indicator (DVDD)
      12. 8.3.12 Power Supplies (VAUX, VDD, VPWR, DVDD)
      13. 8.3.13 Grounds (AGND, GND)
      14. 8.3.14 Output Power Supply (DVDD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Sleep Mode
      2. 8.4.2 Checking VBUS at Start Up
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 System-Level ESD Protection
      2. 9.1.2 Using ENSRC to Enable the Power Supply upon Sink Attachment
      3. 9.1.3 Use of GD Internal Clamp
      4. 9.1.4 Resistor Divider on GD for Programmable Start Up
      5. 9.1.5 Selection of the CTL1, CTL2, and CTL3 Resistors (R(FBL1), R(FBL2), and R(FBL3))
      6. 9.1.6 Voltage Transition Requirements
      7. 9.1.7 VBUS Slew Control using GDNG C(SLEW)
      8. 9.1.8 Tuning OCP using RF and CF
    2. 9.2 Typical Applications
      1. 9.2.1 Typical Application, A/C Power Source (Wall Adapter)
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Power Pin Bypass Capacitors
          2. 9.2.1.2.2 Non-Configurable Components
          3. 9.2.1.2.3 Configurable Components
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Typical Application, D/C Power Source
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Power Pin Bypass Capacitors
          2. 9.2.2.2.2 Non-Configurable Components
          3. 9.2.2.2.3 Configurable Components
        3. 9.2.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 D/C Power Source (Power Hub)
      2. 9.3.2 A/C Power Source (Wall Adapter)
      3. 9.3.3 Dual-Port A/C Power Source (Wall Adaptor)
      4. 9.3.4 D/C Power Source (Power Hub with 3.3 V Rail)
  10. 10Power Supply Recommendations
    1. 10.1 VDD
    2. 10.2 VPWR
  11. 11Layout
    1. 11.1 Port Current Kelvin Sensing
    2. 11.2 Layout Guidelines
      1. 11.2.1 Power Pin Bypass Capacitors
      2. 11.2.2 Supporting Components
    3. 11.3 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 术语表
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.5 Electrical Characteristics

Unless otherwise stated in a specific test condition the following conditions apply: –40°C ≤ TJ ≤ 125°C; 3 ≤ VDD ≤ 5.5 V, 4.65 V ≤ VPWR ≤ 25 V; HIPWR = GND, PSEL = GND, GD = VAUX, PCTRL = VAUX, AGND = GND; VAUX, VTX, bypassed with 0.1 µF, DVDD bypassed with 0.22 µF; all other pins open (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Voltage Comparator (VBUS)
V(VBUS_RTH) VBUS threshold (Rising voltage) 4.25 4.45 4.65 V
V(VBUS_FTH) VBUS threshold (Falling voltage) 3.5 3.7 3.9 V
VBUS threshold (Hysteresis) 0.75 V
Power Supply (VDD, VPWR)
V(VDD_TH) VDD UVLO threshold Rising voltage 2.8 2.91 2.97 V
Falling voltage 2.8 2.86 2.91
Hysteresis, comes into effect once the rising threshold is crossed. 0.05
V(VPWR_RTH) VPWR UVLO threshold rising Rising voltage 4.2 4.45 4.65 V
V(VPWR_FTH) VPWR UVLO threshold falling Falling voltage 3.5 3.7 3.9 V
VPWR UVLO threshold hysteresis Hysteresis, comes into effect once the rising threshold is crossed. 0.75 V
Supply current drawn from VDD in sleep mode VPWR = 0 V, VDD = 5 V, CC1 and CC2 pins are open. 9.2 20 µA
VPWR = 0 V, VDD = 5 V,CC1 pin open, CC2 pin tied to GND. 94 150 µA
Supply current drawn from VPWR in sleep mode VPWR = 5 V, VDD = 0 V, CC1 and CC2 pins are open. 8.5 15 µA
VPWR = 5 V, VDD = 0 V, CC1 pin open, CC2 pin tied to GND. 90 140 µA
I(SUPP) Operating current while sink attached PD Sourcing active, VBUS = 5 V,
VPWR = 5 V, VDD = 3.3 V		 1 1.8 3 mA
Over/Under Voltage Protection (VBUS)
V(FOVP) Fast OVP threshold, always enabled 5 V PD contract 5.8 6.05 6.3 V
9 V PD contract 10.1 10.55 11.0 V
12 V PD contract 13.2 13.75 14.3 V
15 V PD contract 16.2 16.95 17.7 V
20 V PD contract 22.1 23.05 24.0 V
V(SOVP) Slow OVP threshold, disabled during voltage transitions. (See Figure 1) 5 V PD contract 5.5 5.65 5.8 V
9 V PD contract 10 10.2 10.4 V
12 V PD contract 13.1 13.4 13.7 V
15 V PD contract 16.3 16.5 17 V
20 V PD contract 21.5 22.0 22.5 V
V(SUVP) UVP threshold, disabled during voltage transitions (See Figure 1) 5 V PD contract 3.5 3.65 3.8 V
9 V PD contract 6.8 6.95 7.1 V
12 V PD contract 9.2 9.45 9.7 V
15 V PD contract 11.7 11.95 12.2 V
20 V PD contract 15.7 16.1 16.5 V
VAUX
V(VAUX) Output voltage 0 ≤ I(VAUX) ≤ I(VAUXEXT) 2.875 3.2 4.1 V
VAUX current limit 1 5 mA
I(VAUXEXT) External load that may be applied to VAUX. 25 µA
DVDD
V(DVDD) Output voltage 0 mA ≤ I(DVDD) ≤ 35 mA, CC1 or CC2 pulled to ground via 5.1 kΩ, or both CC1 and CC2 pulled to ground via 1 kΩ 1.75 1.85 1.95 V
Load regulation Overshoot from V(DVDD), 10-mA minimum,
0.198-µF bypass capacitor		 1.7 2 V
Current limit DVDD tied to GND 40 150 mA
VTX
Output voltage Not transmitting or receiving, 0 to 2 mA external load 1.050 1.125 1.200 V
Current limit VTX tied to GND 2.5 10 mA
Gate Driver Disable (GD)
V(GD_TH) Input enable threshold voltage Rising voltage 1.64 1.725 1.81 V
Hysteresis 0.15 V
V(GDC) Internal clamp voltage I(GD) = 80 µA 6.5 7 8.5 V
R(GD) Internal pulldown resistance From 0 V to 6 V 3 6 9.5 MΩ
Discharge (DSCG)(1)(2)
V(DSCGT) ON state (linear) I(DSCG) = 100 mA 0.15 0.42 1 V
I(DSCGT) ON state (saturation) V(DSCG) = 4 V, pulsed mode operation 220 553 1300 mA
R(DSCGB) Discharge bleeder While CC1 is pulled down by 5.1 kΩ and CC2 is open, V(DSCG) = 25 V 6.6 8.2 10 kΩ
Leakage current 0 V ≤ V(DSCG) ≤ 25 V 2 µA
N-ch MOSFET Gate Driver (GDNG,GDNS)
I(GDNON) Sourcing current 0 V ≤ V(GDNS) ≤ 25 V,
0 V ≤ V(GDNG) – V(GDNS) ≤ 6 V		 13.2 20 30 µA
V(GDNON) Sourcing voltage while enabled
(V(GDNG)– V(GDNS))		 0 V ≤ V(GDNS) ≤ 25 V, I(GDNON) ≤ 4 µA, VDD = 0 V 8.5 12 V
R(GDNGOFF) Sinking strength while disabled V(GDNG) – V(GDNS)= 0.5 V,
0 ≤ V(GDNS) ≤ 25 V		 150 300 Ω
Sinking strength UVLO (safety) VDD = 1.4 V, V(GDNG) = 1 V,
V(GDNS) = 0 V, VPWR = 0 V		 145 µA
VPWR = 1.4 V, V(GDNG) = 1 V,
V(GDNS) = 0 V, VDD = 0 V		 145 µA
Off-state leakage V(GDNS) = 25 V, V(GDNG) open 7 µA
Power Control Input (PCTRL)
V(PCTRL_TH) Threshold voltage(3) Voltage rising 1.65 1.75 1.85 V
Hysteresis 100 mV
Input resistance 0 V ≤ V(PCTRL) ≤ V(VAUX) 1.5 2.9 6 MΩ
Voltage Select (HIPWR), Power Select (PSEL)(4)
Leakage current 0 V ≤ V(HIPWR) ≤ V(DVDD),
0 V ≤ V(PSEL) ≤ V(DVDD) 		–1 1 µA
Port Status and Voltage Control (CTL1, CTL2, CTL3, ENSRC)(5)
VOL Output low voltage IOL = 4 mA sinking 0.4 V
Leakage current (6) In Hi-Z state, 0 ≤ V(CTLx) ≤ 5.5 V or
0 ≤ VENSRC ≤ 5.5V		 –0.5 0.5 µA
Transmitter Specifications (CC1, CC2)
RTX Output resistance (zDriver from USB PD in 文档支持) During transmission 33 45 75 Ω
V(TXHI) Transmit high voltage External Loading per Figure 27 1.05 1.125 1.2 V
V(TXLO) Transmit low voltage External Loading per Figure 27 –75 75 mV
Receiver Specifications (CC1, CC2)
V(RXHI) Receive threshold (rising) 800 840 885 mV
V(RXLO) Receive threshold (falling) 485 525 570 mV
Receive threshold (Hysteresis) 315 mV
V(INT) Amplitude of interference that can be tolerated Interference is 600 kHz square wave, rising 0 to 100 mV. 100 mV
Interference is 1 MHz sine wave 1 VPP
DFP Specifications (CC1, CC2)
V(DSTD) Detach threshold when cable is detached. In standard Rp mode(7), voltage rising 1.52 1.585 1.65 V
Hysteresis 0.02 V
V(D1.5) In 1.5 A Rp mode(8), voltage rising 1.52 1.585 1.65 V
Hysteresis 0.02 V
V(D3.0) In 3 A Rp mode(9), voltage rising 2.50 2.625 2.75 V
Hysteresis 0.05 V
V(OCN) Unloaded output voltage on CC pin normal mode 2.75 4.35 V
V(OCDS) VPWR = 0 V (in UVLO) or in sleep mode 1.8 5.5 V
I(RPSTD) Loaded output current while connected through CCx In standard Rp mode1, CCy open,
0 V ≤ VCCx ≤ 1.5 V (vRd)		 64 80 96 µA
I(RP1.5) In 1.5 A Rp mode 2, CCy open,
0 V ≤ VCCx ≤ 1.5 V (vRd)		 166 180 194 µA
I(RP3.0) In 3 A Rp mode 3, CCy open,
0 V ≤ VCCx ≤ 1.5 V (vRd)		 304 330 356 µA
V(RDSTD) Ra, Rd detection threshold (falling) In standard Rp mode1,
0 V ≤ VCCx ≤ 1.5 V (vRd)		 0.15 0.19 0.23 V
Hysteresis 0.02 V
V(RD1.5) In 1.5 A Rp mode2, CCy open
0 V ≤ VCCx ≤ 1.5 V (vRd)		 0.35 0.39 0.43 V
Hysteresis 0.02 V
V(RD3.0) In 3 A Rp mode3, CCy open
0 V ≤ VCCx ≤ 1.5 V (vRd)		 0.75 0.79 0.83 V
Hysteresis 0.02 V
V(WAKE) Wake threshold (rising and falling), exit from sleep mode VPWR = 4.65 V , 0 V ≤ VDD ≤ 3 V(10) 1.6 3.0 V
I(DSDFP) Output current on CCx in sleep mode to detect Ra removal CCx = 0V, CCy floating 40 73 105 µA
OverCurrent Protection (ISNS, VBUS)
VI(TRIP) Current trip shunt voltage Specified as V(ISNS)-V(VBUS).
3.5 V(11) ≤ VBUS ≤ 25 V
HIPWR: 5 A not enabled 19.2 22.6 mV
HIPWR = DVDD (5 A enabled) 29 34 mV
OTSD
TJ1 Die temperature (Analog)(12) TJ ↑ 125 135 145 °C
Hysteresis 10
TJ2 Die temperature (Analog) (13) TJ ↑ 140 150 163 °C
Hysteresis 10
(1) If TJ1 is perceived to have been exceeded an OTSD occurs and the discharge FET is disabled.
(2) The discharge pull-down is not active in the sleep mode.
(3) When voltage on the PCTRL pin is less than V(PCTRL_TH), the amount of power advertised is reduced by half.
(4) Leaving HIPWR or PSEL open is an undetermined state and leads to unpredictable behavior.
(5) These pins are high-z during a UVLO, reset, or in Sleep condition.
(6) The pins were designed for less leakage, but testing only verifies that the leakage does not exceed 0.5 µA.
(7) Standard Rp mode is active after a USB Type-C sink, debug accessory, or audio accessory is attached until the first USB PD message is transmitted (after GDNG has been enabled).
(8) 1.5 A Rp mode is active after a USB PD message is received.
(9) 3 A Rp mode is active after GDNG has been enabled until a USB PD message is received.
(10) VWAKE < VOCDS is always true.
(11) Common mode minimum aligns to VBUS UVLO. VBUS must be above its UVLO for the OCP function to be active.
(12) When TJ1 trips a hard reset is transmitted and discharge is disabled, but the bleed discharge is not disabled.
(13) TJ2 trips only when some external heat source drives the temperature up. When it trips the DVDD, and VAUX power outputs are turned off.
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