米6体育平台手机版

ZHCSFH8D August 2016 – January 2018 TPS25741 , TPS25741A

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

RSM|32
- MPQF195B

散热焊盘机械数据 (封装 | 引脚)

RSM|32
- QFND112H

订购信息

7.5 Electrical Characteristics

Unless otherwise stated in a specific test condition the following conditions apply: –40°C ≤ T_J ≤ 125°C; 3 ≤ VDD ≤ 5.5 V, 4.65 V ≤ VPWR ≤ 25 V; HIPWR = GND, PSEL = GND, GD = VAUX, PCTRL = VAUX, AGND = GND;EN9V = GND; EN12V = GND; VAUX, VTX, bypassed with 0.1 µF, DVDD bypassed with 0.22 µF; all other pins open (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
Voltage Comparator (VBUS)
V_{BUS_RTH}	VBUS Threshold (Rising voltage)		4.25	4.45	4.65	V
V_{BUS_FTH}	VBUS Threshold (Falling voltage)		3.5	3.7	3.9	V
	VBUS Threshold (Hysteresis)			0.75		V
Power Supply (VDD, VPWR)
V_{DD_TH}	VDD UVLO threshold	Rising voltage	2.8	2.91	2.97	V
		Falling voltage	2.8	2.86	2.91
		Hysteresis, comes into effect once the rising threshold is crossed.		0.05
V_{PWR_TH}	VPWR UVLO threshold	Rising voltage	4.2	4.45	4.65	V
		Falling voltage	3.5	3.7	3.9
		Hysteresis, comes into effect once the rising threshold is crossed.		0.75
	Supply current drawn from VDD in sleep mode	VPWR = 0 V, VDD = 5 V, CC1 and CC2 pins are open. T_J = 25°C		8.5		µA
		VPWR = 0 V, VDD = 3.3 V, CC1 and CC2 pins are open. T_J = 25°C		5.4		µA
		VPWR = 0 V, VDD = 5 V,CC1 pin open, CC2 pin tied to GND. T_J = 25°C		93		µA
	Supply current drawn from VPWR in sleep mode	VPWR = 5 V, VDD = 0 V, CC1 and CC2 pins are open. T_J = 25°C		8		µA
	Supply current drawn from VPWR in sleep mode	VPWR = 5 V, VDD = 0 V, CC1 pin open, CC2 pin tied to GND. T_J = 25°C		89		µA
I_SUPP	Typical operating current (from VPWR and VDD)	Power Delivery Sourcing active, VBUS = 5 V, VPWR = 5 V, VDD = 3.3 V	1	1.8	3	mA
Over/Under Voltage Protection (VBUS)
V_FOVP	Fast OVP threshold, always enabled	5 V Power Delivery contract	5.8	6.05	6.3	V
		12 V Power Delivery contract (TPS25741)	13.2	13.75	14.3	V
		20 V Power Delivery contract (TPS25741)	22.1	23.05	24.0	V
		9 V Power Delivery contract (TPS25741A)	10.1	10.55	11.0	V
		15 V Power Delivery contract (TPS25741A)	16.2	16.95	17.7	V
V_SOVP	Slow OVP threshold, disabled during voltage transitions. (see Figure 1)	5 V Power Delivery contract	5.5	5.65	5.8	V
		12 V Power Delivery contract (TPS25741)	13.1	13.4	13.7	V
		20 V Power Delivery contract (TPS25741)	21.5	22.0	22.5	V
		9 V Power Delivery contract (TPS25741A)	10	10.2	10.4	V
		15 V Power Delivery contract (TPS25741A)	16.3	16.5	17	V
V_SUVP	UVP threshold, disabled during voltage transitions (see Figure 1)	5 V Power Delivery contract	3.5	3.65	3.8	V
		12 V Power Delivery contract (TPS25741)	9.2	9.45	9.7	V
		20 V Power Delivery contract (TPS25741)	15.7	16.1	16.5	V
		9 V Power Delivery contract (TPS25741A)	6.8	6.95	7.1	V
		15 V Power Delivery contract (TPS25741A)	11.7	11.95	12.2	V
VAUX
V_VAUX	Output voltage	0 ≤ I_VAUX ≤ I_VAUXEXT	2.875	3.2	4.1	V
	VAUX Current limit		1		5	mA
I_VAUXEXT	External load that may be applied to VAUX.				25	µA
DVDD
V_DVDD	Output voltage	0 mA ≤ I_DVDD ≤ 35 mA, CC1 or CC2 pulled to ground via 5.1 kΩ, or both CC1 and CC2 pulled to ground via 1 kΩ	1.75	1.85	1.95	V
	Load Regulation	Overshoot from V_DVDD, 10-mA minimum, 0.198-µF bypass capacitor	1.7		2	V
	Load Regulation	Undershoot from V_DVDD, 10-mA minimum, 0.198-µF bypass capacitor	1.7		2	V
	Current limit	DVDD tied to GND	40		150	mA
VTX
	Output voltage	Not transmitting or receiving, 0 to 2 mA external load	1.050	1.125	1.200	V
	Current Limit	VTX tied to GND	2.5		10	mA
Gate Driver Disable (GD)
V_{GD_TH}	Input enable threshold voltage	Rising voltage	1.64	1.725	1.81	V
V_{GD_TH}	Input enable threshold voltage	Hysteresis		0.15		V
V_GDC	Internal clamp voltage	I_GD = 80 µA	6.5	7.5	8.5	V
R_GD	Internal pulldown resistance	From 0 V to 6 V	3	6	9.5	MΩ
Discharge (DSCG)⁽¹⁾⁽²⁾
V_DSCGT	ON state (linear)	I_DSCG = 100 mA	0.15	0.42	1	V
I_DSCGT	ON state (saturation)	V_DSCG = 4 V, pulsed testing	220	553	1300	mA
R_DSCGB	Discharge bleeder	While CC1 is pulled down by 5.1 kΩ and CC2 is open, V_DSCG = 25 V, compute V_DSCG/I_DSCG	6.6	8.2	10	kΩ
	Leakage current	0 V ≤ V_DSCG ≤ 25 V			2	µA
P-ch MOSFET Gate Driver (GDPG)
I_GDPG	Sinking current (ON)	2 V ≤ V_GDPG ≤ 25 V	34	41	48	µA
I_LGDPG	Leakage current	0 V ≤ V_GDPG ≤ 25 V			2	µA
N-ch MOSFET Gate Driver (G5V)
I_G5VON	Sourcing current	0 V ≤ V_G5V ≤ 9 V	6.6	10		µA
V_G5VON	Sourcing voltage (ON)	I_G5V ≤ 2 µA	10		16	V
R_G5VOFF	Sinking strength (OFF)	V_G5V = 1 V			200	Ω
	Sinking strength UVLO (safety)	V_DD = 1.3 V, V_PWR = 0 V, V_G5V = 1 V		288		µA
	Sinking strength UVLO (safety)	V_PWR = 1.3 V, V_DD = 0 V, V_G5V = 1 V		343		µA
	Off-state leakage	V_G5V = 15V			2	µA
N-ch MOSFET Gate Driver (GDNG,GDNS)
I_GDNGON	Sourcing current	0 V ≤ V_GDNS ≤ 25 V, 0 V ≤ V_GDNG – V_GDNS ≤ 6 V	13.2	20	30	µA
V_GDNGON	Sourcing voltage while enabled (V_GDNG – V_GDNS)	0 V ≤ V_GDNS ≤ 25 V, I_GDNGON ≤ 4 µA, VPWR = 0 V	7		12	V
V_GDNGON	Sourcing voltage while enabled (V_GDNG – V_GDNS)	0 V ≤ V_GDNS ≤ 25 V, I_GDNGON ≤ 4 µA, VDD = 0 V	8.5		12	V
R_GDNGOFF	Sinking strength while disabled	V_GDNG – V_GDNS= 0.5 V, 0 ≤ V_GDNS ≤ 25 V		150	300	Ω
	Sinking strength UVLO (safety)	VDD = 1.4 V, V_GDNG = 1 V, V_GDNS = 0 V, VPWR = 0 V		145		µA
	Sinking strength UVLO (safety)	VDD = 1.4 V, V_GDNG = 1 V, V_GDNS = 0 V, VDD = 0 V		145		µA
	Off-state leakage	V_GDNS = 25 V, V_GDNG open			7	µA
Power Control Input (PCTRL)
V_{PCTRL_TH}	Active threshold voltage⁽³⁾	Voltage rising	1.65	1.75	1.85	V
V_{PCTRL_TH}	Active threshold voltage⁽³⁾	Hysteresis		100		mV
	Input resistance	0 V ≤ V_PCTRL ≤ V_VAUX	1.5	2.9	6	MΩ
Voltage Select (HIPWR), Power Select (PSEL)⁽⁴⁾
	Leakage current	0 V ≤ V_HIPWR ≤ V_DVDD, 0 V ≤ V_PSEL ≤ V_DVDD	–1		1	µA
Port Status and Voltage Control (CTL1, CTL2, UFP, POL, DEBUG)⁽⁵⁾
V_OL	Output low voltage	I_OL = 4 mA sinking			0.4	V
	Leakage Current ⁽⁶⁾	In Hi-Z state, 0 ≤ V_CTLx ≤ 5.5 V or 0 ≤ V_UFP ≤ 5.5V	–0.5		0.5	µA
Presence of Audio Accessory (AUDIO)⁽¹³⁾
I_AUD	Current pull down	V_AUDIO = 1 V	34	40	46	kΩ
	Leakage current	0 V ≤ V_AUDIO ≤ 5.5 V			2	µA
Enable 9 V, 12 V Capability (EN9V, EN12V)⁽⁷⁾
V_ILGIO	Input low threshold voltage				0.585	V
V_IHGIO	Input high threshold voltage		1.225			V
	Input hysteresis			0.25		V
Transmitter Specifications (CC1, CC2)
R_TX	Output resistance (zDriver, refer to USB Power Delivery in Documentation Support)	During transmission	33	48	75	Ω
V_TXHI	Transmit high voltage	External Loading per Figure 28	1.05	1.125	1.2	V
V_TXLO	Transmit low voltage	External Loading per Figure 28	–75		75	mV
Receiver Specifications (CC1, CC2)
V_RXHI	Receive threshold (rising)		800	840	885	mV
V_RXLO	Receive threshold (falling)		485	525	570	mV
	Receive threshold (hysteresis)			315		mV
	Amplitude of interference that can be tolerated.	Interference is 600 kHz square wave, rising 0 to 100 mV.			100	mV
	Amplitude of interference that can be tolerated.	Interference is 1 MHz sine wave			1	V_PP
DFP Specifications (CC1, CC2)
V_DSTD	Detach threshold when cable is detached while in standard DFP mode.	In standard DFP mode⁽⁸⁾, voltage rising	1.52	1.585	1.65	V
V_DSTD		Hysteresis		0.02		V
V_D1p5	Detach threshold when cable is detached.	In 1.5 A DFP mode⁽⁹⁾, voltage rising	1.52	1.585	1.65	V
V_D1p5	Detach threshold when cable is detached.	Hysteresis		0.02		V
V_D3p0	Detach threshold when cable is detached	In 3 A DFP mode⁽¹⁰⁾, voltage rising	2.50	2.625	2.75	V
V_D3p0	Detach threshold when cable is detached	Hysteresis		0.05		V
V_OCN	Unloaded output voltage on CC pin	normal mode	2.7		4.35	V
V_OCDS		V_PWR = 0 V (in UVLO) or in sleep mode	1.8		5.5	V
I_RPSTD	Loaded output current while connected through CCx	In standard DFP mode⁽⁸⁾, CCy open, 0 V ≤ V_CCx ≤ 1.5 V (vRd)	64	80	96	µA
I_RP1.5	Loaded output current while connected through CCx	In 1.5 A DFP mode⁽⁹⁾, CCy open, 0 V ≤ V_CCx ≤ 1.5 V (vRd)	166	180	194	µA
I_RP3.0	Loaded output current while connected through CCx	In 3 A DFP mode⁽¹⁰⁾, CCy open, 0 V ≤ V_CCx ≤ 1.5 V (vRd)	304	330	356	µA
V_RDSTD	Ra, Rd detection threshold (falling)	In standard DFP mode⁽⁸⁾, 0 V ≤ V_CCx ≤ 1.5 V (vRd)	0.15	0.19	0.23	V
V_RDSTD	Ra, Rd detection threshold (falling)	Hysteresis		0.02		V
V_RD1.5	Ra, Rd detection threshold (falling)	In 1.5 A DFP mode⁽⁹⁾, CCy open 0 V ≤ V_CCx ≤ 1.5 V (vRd)	0.35	0.39	0.43	V
V_RD1.5	Ra, Rd detection threshold (falling)	Hysteresis		0.02		V
V_RD3.0	Ra, Rd detection threshold (falling)	In 3 A DFP mode⁽¹⁰⁾, CCy open 0 V ≤ V_CCx ≤ 1.5 V (vRd)	0.75	0.79	0.83	V
V_RD3.0	Ra, Rd detection threshold (falling)	Hysteresis		0.02		V
V_WAKE	Wake threshold (rising and falling), exit from sleep mode	VPWR = 4.65 V , 0 V ≤ VDD ≤ 3 V	1.6		3.0	V
I_DSDFP	Output current on CCx in sleep mode to detect Ra removal.	CCx = 0V, CCy floating	40	73	105	µA
Connector Power Specifications (CC1, CC2, VCONN)⁽¹⁶⁾
	UVLO for VCONN ⁽¹⁸⁾	Turn-on, VCONN rising	2.2	2.4	2.6	V
	UVLO for VCONN ⁽¹⁸⁾	Hysteresis		0.1		V
R_DSON	Resistance from VCONN to CC1 or CC2⁽¹⁴⁾⁽¹⁷⁾	4.75 V ≤ V_CONN ≤ 5.5 V (Fixed Supply mode), I_CCx = 250 mA –40°C ≤ T_J ≤ 125°C		300	500	mΩ
R_DSON	Resistance from VCONN to CC1 or CC2⁽¹⁴⁾⁽¹⁷⁾	4.75 V ≤ V_CONN ≤ 5.5 V (Fixed Supply mode), I_CCx = 250 mA T_J = 25°C		300	350	mΩ
I_OS	Current limit measured on CC1 or CC2⁽¹⁵⁾	4.75 V ≤ V_CONN ≤ 5.5 V (Fixed Supply mode)	415	490	562	mA
	Fault threshold		1.1×I_OS		1.25×I_OS	mA
Over-Current Protection (ISNS, VBUS)
V_ITRIP	Current trip shunt voltage	Specified as V_ISNS – V_BUS. The OCP trip point setting assumes the sense resistor is 5 mΩ
		HIPWR: 5 A not enabled	19.2		22.6	mV
		HIPWR: 5 A enabled	29		34	mV
OTSD
T_J1	Die Temperature (Analog)⁽¹¹⁾	T_J ↑	125	135	145	°C
T_J1	Die Temperature (Analog)⁽¹¹⁾	Hysteresis		10		°C
T_J2	Die Temperature (Analog)⁽¹²⁾	T_J ↑	140	150	163	°C
T_J2	Die Temperature (Analog)⁽¹²⁾	Hysteresis		10		°C

(1) If T_J1 is perceived to have been exceeded an OTSD occurs and the discharge FET is disabled.

(2) The discharge pull-down is not active in the sleep mode.

(3) When voltage on the PCTRL pin is less than V_{(PCTRL_TH)}, the amount of power advertised is reduced by half.

(4) Leaving HIPWR or PSEL open is an undetermined state and leads to unpredictable behavior.

(5) These pins are high-z during a UVLO, reset, or in Sleep condition.

(6) The pins were designed for less leakage, but testing only verifies that the leakage does not exceed 1 µA.

(7) Protection is provided against a voltage greater than V_DVDD being applied externally.

(8) Standard DFP mode is active after a USB Type-C sink, debug accessory, or audio accessory is attached until the first USB Power Delivery message is transmitted (after GDNG has been enabled).

(9) 1.5 A DFP mode is active after a USB Power Delivery contract has been negotiated.

(10) 3 A DFP mode is active after GDNG has been enabled until a USB Power Delivery message is received.

(11) When T_J1 trips a hard reset is transmitted and discharge is disabled, but the bleeder discharge is not disabled.

(12) T_J2 trips only when some external heat source drives the temperature up. When it trips the DVDD, and VAUX power outputs are turned off.

(13) AUDIO is high-z during a UVLO, reset, or Device Sleep condition.

(14) Based on 120 mV drop at 250 mA (to deliver more than 1 W at VCONN = 4.75 V).

(15) While providing VCONN power, the CCx output is monitored for faults (overloads). Thermal shutdown is provided with thermal cycling (auto-restart).

(16) VCONN is always applied when a UFP is attached, regardless of whether Ra is detected.

(17) There are requirements for the VCONN voltage supplied to CC1 or CC2 in [1]; customers need to take the R_DSON into account when designing to meet those requirements.

(18) The VCONN pin has reverse blocking.