ZHCSFH8D August 2016 – January 2018 TPS25741 , TPS25741A
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
There are two types of faults that cause the TPS25741 or TPS25741A to begin a full discharge of VBUS: Slow-shutdown faults and fast-shutdown faults. When a slow-shutdown fault occurs, the device does not disable GDNG until after VBUS is measured below VSOVP (for 5 V contract). When a fast-shutdown fault occurs, the device disables GDNG immediately and then discharges the connector side of the power-path. In both cases, the bleed discharge is applied to the DSCG pin and ISUPP is drawn from the VPWR pin.
Slow-shutdown faults that do not include transmitting a hard reset:
Slow-shutdown faults that include transmitting hard reset (25 ms < tShutdownDelay< 35 ms)
Fast-shutdown faults (hard reset always sent):
The DSCG pin is used to discharge the supply line after a slow-shutdown fault occurs. Figure 32 illustrates the signals involved. Depending on the specific slow-shutdown fault the time tShutdownDelay in Figure 32 is different as indicated in the list above. If the slow-shutdown fault triggers a hard reset, it is sent at the beginning of the tShutdownDelay period. However, the device behavior after the time tShutdownDelay is the same for all slow-shutdown faults. After the tShutdownDelay period, the device sets CTL1 and CTL2 to select 5 V from the power supply and puts the DSCG pin into its ON state (Full Discharge). This discharging continues until the voltage on the VBUS pin reaches VSOPV (for 5 V contract). The device then disables GDNG and again puts the DSCG pin into its ON state. This discharging state lasts until the voltage on VBUS reaches 0.725 V (nominal). If the discharge does not complete within 650 ms, then the device sends a Hard Reset signal and the process repeats. In Figure 32, the times labeled as T20->5 and T5->0 can vary, they depend on the size of the capacitance to be discharged and the size of the external resistor between the DSCG pin and VBUS. The time labeled as TS is a function of how quickly the NFET opens.
Figure 33 illustrates a similar discharge procedure for fast-shutdown faults. The main difference from Figure 32 is that the NFET is opened immediately. It is assumed for the purposes of this illustration that the power supply output capacitance (that is, CSOURCE in the reference schematics shown in Figure 20 and Figure 21) is not discharged by the power supply itself, but the VPWR pin is bleeding current from that capacitance. The VPWR pin then draws ISUPP after GDNG disables the external NFET. So, as shown in the figure, the VPWR voltage discharges slowly, while the VBUS pin is discharged quickly once the full discharge is enabled. If the voltage on the VPWR pin takes longer than T20->5 + T5->0 + 0.765s to discharge below VFOVP, then it causes an OVP event and the process repeats.
If the discharge does not complete successfully it is treated as a slow-shutdown fault, and the TPS25741 or TPS25741A repeats the discharge procedure until it does complete successfully. Once the discharge completes successfully as described above (that is, VBUS on connector is below 0.725 V), the device waits for 0.765 s (nominal) before trying to source VBUS again.