ZHCSFH8D August 2016 – January 2018 TPS25741 , TPS25741A
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
As described in the Configuring Power Capabilities (PSEL, PCTRL, HIPWR) section, the GD pin has an internal clamp. Figure 43 shows an example of how it may be used. VOUT is the voltage from a power supply that is to be provided onto the VBUS wire of the USB Type-C cable through an NFET. If VOUT drops, the NFET should be automatically disabled by the device. This can be accomplished by tying the GD pin to VOUT via a resistor.
The internal resistance of the GD pin is specified to exceed RGD, and the input threshold is VGD_TH. The GD pin would therefore draw no more than VGD_TH(max) / RGD(min) < 603 nA. As an example, assume the minimum value of VOUT for which GD should be high is 4.5 V, then the resistor between GD and VOUT may not exceed (4.5 – VGD_TH(max) / 603e-9 = 4.5 MΩ. To make it robust against board leakage a smaller resistor such as 1 MΩ can be chosen, but the smaller the resistance the more leakage current into the GD pin. In this example, when VOUT is 25 V, the current into the GD pin is (25-VGDC) / 1e6 < 18.5 µA.