9.1.5 Voltage Transition Requirements

During VBUS voltage transitions, the slew rate (v_SrcSlewPos in USB in Documentation Support) must be kept below 30 mV/µs in all portions of the waveform, settle (t_SrcSettle) in less than 275 ms, and be ready (t_SrcReady in USB in Documentation Support) in less than 285 ms. For most power supplies, these requirements are met naturally without any special circuitry but in some cases, the voltage transition ramp rate must be slowed in order to meet the slew rate requirement.

The requirements for linear voltage transitions are shown in Table 7. In all cases, the minimum slew time is below 1 ms.

When transition slew control is required, the interaction of the slew mechanism and dc/dc converter loop response must be considered. A simple R-C filter between the device CTL pins and converter feedback node may lead to instability under some conditions. Figure 46 shows a method which manages the slew control without adding capacitance to the converter feedback node.

When V_OUT = 5 V, both CTL1 and CTL2 are in a high impedance state. When a 5 V to 12 V transition is requested, CTL2 goes low and turns off Q_CTL2. Q_SL2 gate starts to rise towards VCC at a rate determined by R_SL2A + R_SL2B and C_SL2. Q_SL2 gate continues to rise, until Q_SL2 is fully enhanced placing R_FBL2 in parallel with R_FBL. In similar fashion when CTL1 goes low, Q_CTL1 turns off allowing R_FBL1 to slew in parallel with R_FBL2 and R_FBL.

The slewing resistors and capacitor can be chosen using the following equations. V_T is the V_GS threshold voltage of Q_SL1 and Q_SL2. V_REF is the feedback regulator reference voltage. Choose the slewing resistance in the 100 kΩ range to reduce the loading on the bias voltage source (VCC) and then calculate C_SL. The falling transitions are shorter than the rising transitions in this topology.

Falling transitions:

• 20 V to 12 V

• 12 V to 5 V

Rising transitions:

• 5 V to 12 V

• 12 V to 20 V

Some converter regulators can tolerate a balance of capacitance on the feedback node without affecting loop stability. The LM5175 has been tested using Figure 47 to combine V_OUT slewing with a minimal amount of extra circuitry.

When a higher voltage is requested from TPS25741, CTL1 or CTL2 goes low changing the sensed voltage at the FB pin. The LM5175 compensates by increasing V_OUT. As V_OUT increases, C_SLU is charged at a rate proportional to R_FBU. Three time constants yield a voltage change of approximately 95% and can be used to calculate the desired slew time. C_SLU can be calculated using Equation 10 and Equation 11.

In order to minimize loop stability effects, a capacitor C_SLL in parallel with R_FBL is required. The ratio of C_SLU/C_SLL should be chosen to match the ratio of R_FBL/R_FBU. Choose C_SLL according to Equation 12.

All slew rate control methods should be verified on the bench to ensure that the slew rate requirements are being met when the external VBUS capacitance is between 1 μF and 100 μF.