9.1.6 V_BUS Slew Control using GDNG C_SLEW

Care should be taken to control the slew rate of Q1 using C_SLEW; particularly in applications where C_OUT>> C_SLEW. The slew rate observed on V_BUS when charging a purely capacitive load is the same as the slew rate of V_GDNG and is dominated by the ratio I_GDNGON /C_SLEW. R_SLEW helps block C_SLEW from the GDNG pin enabling a faster transient response to OCP.

Figure 48. Slew-Rate Control Using GDNG

There may be fault conditions where the voltage on V_BUS triggers an OVP condition and then remains at a high voltage even after the TPS25741 configures the voltage source to output 5 V via CTL1 and CTL2. When this OVP occurs, the TPS25741 opens Q1 within t_FOVP + t_FOVPDG. The TPS25741 then issues a hard reset, discharges the power-path via the R_DSCG, and waits for 795 ms before enabling Q1 again. Due to the fault condition the voltage again triggers an OVP event when the voltage on V_BUS exceeds V_FOVP. This retry process would continue as long as the fault condition persists, periodically pulsing up to V_FOVP + V_SrcSlewPos x (t_FOVP + t_FOVPDG) onto the V_BUS of the Type-C receptacle. It is recommended to use a slew rate less than the maximum of V_SrcSlewPos (30 mV/µs), refer to Documentation Support section, the slew rate should instead be set in order to meet the requirement to have the voltage reach the target voltage within t_SrcSettle (275 ms) (refer to USB Power Delivery in Documentation Support). This also limits the out-rush current from the C_OUT capacitor into the C_PDIN capacitor and helps protect Q1 and R_S.