Three internal LDOs provide regulated supplies for operation of internal circuitry.

• LDO_5V: Supplies buck-boost gate drive circuitry, LDO_3V3, LDO_1V5, and PA and PB VCONN power paths. External bypass capacitance, C_{LDO_5V} is required for proper operation. It is highly recommended to include an additional high frequency 0.1 μF capacitor in parallel with C_{LDO_5V}. C_{LDO_5V} and the parallel high frequency should be placed as close to the LDO_5V pin as possible. This capacitance: 1) provides energy storage for the buck-boost internal FET gate drivers, and 2) is required to stabilize the internal 5-V LDO in applications where an external 5-V supply is not connected. The TPS25772-Q1 will not operate (release reset) until V_{LDO_5V(UVLO_R)} threshold is met. Hard reset occurs when V_{LDO_5V} < V_{LDO_5V(UVLO_F)} threshold. Current from LDO_5V returns to PGND pin. The LDO_5V output may be used to supply a small external loads such as indicator LEDs. When supplying external components, it is recommended that the total external load current not exceed 25 mA (MAX).
  • 0.1W VCONN: when enabled in the application configuration GUI, LDO_5V is capable of sourcing 20 mA each to PA_VCONN and PB_VCONN.
  • 1W VCONN: when enabled in the application configuration GUI, this mode of operation requires an external 4.75 - 5.5 V, 500-mA capable supply connected to LDO_5V. Back-feeding of LDO_5V is allowed.
• LDO_3V3: Supplies internal analog circuits, GPIO buffers, USB PD and the USB Endpoint PHYs. External bypass capacitance of C_{LDO_3V3} is required for proper operation. An additional 0.1 μF capacitor in parallel with C_{LDO_3V3} is highly recommended to filter high frequency noise from the I/O buffers and PHYs. The LDO_3V3 can supply external circuits at up to 25 mA. Expected loads include: EEPROM (5mA), NTC resistor divider network (< 1 mA). Current may be drawn up to I_{LDO_3V3(ILIMIT)}. Note: the USB PD and Endpoint PHYs draw current from LDO_3V3. If a CCx or Dx pin is shorted to GND during a transmission the current drawn may reach the current limit threshold. Similarly, if any GPIO pins are configured as push-pull outputs and a GPIO short to GND event occurs, the LDO_3V3 current limit may be reached. Current returns to AGND pin.
• LDO_1V5: Supplies digital core. External bypass capacitance of C_{LDO_1V5} is required for proper operation. An additional 0.1 μF capacitor in parallel with C_{LDO_1V5} is highly recommended to filter noise generated by the digital core. The M0 is held in reset until all three UVLO_R (rising) thresholds are met. Current returns to AGND pin.

Figure 9-3 Internal LDO Connection Diagram