ZHCSLL2A May   2021  – March 2022 TPS25830A-Q1 , TPS25832A-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 说明（续）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Switching Characteristics
    8. 8.8 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Buck Regulator
      2. 10.3.2  Enable/UVLO and Start-Up
      3. 10.3.3  Switching Frequency and Synchronization (RT/SYNC)
      4. 10.3.4  Spread-Spectrum Operation
      5. 10.3.5  VCC, VCC_UVLO
      6. 10.3.6  Minimum ON-Time, Minimum OFF-Time
      7. 10.3.7  Internal Compensation
      8. 10.3.8  Bootstrap Voltage (BOOT)
      9. 10.3.9  RSNS, RSET, RILIMIT and RIMON
      10. 10.3.10 Overcurrent and Short Circuit Protection
        1. 10.3.10.1 Current Limit Setting using RILIMIT
        2. 10.3.10.2 Current Limit Setting for MFI OCP
        3. 10.3.10.3 Buck Average Current Limit Design Example
        4. 10.3.10.4 External MOSFET Gate Drivers
        5. 10.3.10.5 Cycle-by-Cycle Buck Current Limit
      11. 10.3.11 Overvoltage, IEC and Short to Battery Protection
        1. 10.3.11.1 VBUS and VCSN/OUT Overvoltage Protection
        2. 10.3.11.2 DP_IN and DM_IN Protection
        3. 10.3.11.3 CC IEC and OVP Protection
      12. 10.3.12 Cable Compensation
        1. 10.3.12.1 Cable Compensation Design Example
      13. 10.3.13 USB Port Control
      14. 10.3.14 FAULT Response
      15. 10.3.15 USB Specification Overview
      16. 10.3.16 USB Type-C® Basics
        1. 10.3.16.1 Configuration Channel
        2. 10.3.16.2 Detecting a Connection
        3. 10.3.16.3 Configuration Channel Pins CC1 and CC2
        4. 10.3.16.4 Current Capability Advertisement and VCONN Overload Protection
        5. 10.3.16.5 Plug Polarity Detection
      17. 10.3.17 Device Power Pins (IN, CSN/OUT, and PGND)
      18. 10.3.18 Thermal Shutdown
      19. 10.3.19 Power Wake
    4. 10.4 Device Functional Modes
      1. 10.4.1 Shutdown Mode
      2. 10.4.2 Standby Mode
      3. 10.4.3 Active Mode
      4. 10.4.4 Device Truth Table (TT)
      5. 10.4.5 USB Port Operating Modes
        1. 10.4.5.1 USB Type-C® Mode
        2. 10.4.5.2 Standard Downstream Port (SDP) Mode — USB 2.0, USB 3.0, and USB 3.1
        3. 10.4.5.3 Charging Downstream Port (CDP) Mode
        4. 10.4.5.4 Client Mode
      6. 10.4.6 High-Bandwidth Data-Line Switches
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1  Output Voltage
        2. 11.2.2.2  Switching Frequency
        3. 11.2.2.3  Inductor Selection
        4. 11.2.2.4  Output Capacitor Selection
        5. 11.2.2.5  Input Capacitor Selection
        6. 11.2.2.6  Bootstrap Capacitor Selection
        7. 11.2.2.7  VCC Capacitor Selection
        8. 11.2.2.8  Enable and Undervoltage Lockout Set-Point
        9. 11.2.2.9  Current Limit Set-Point
        10. 11.2.2.10 Cable Compensation Set-Point
        11. 11.2.2.11 LD_DET, POL, and FAULT Resistor Selection
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Ground Plane and Thermal Considerations
    3. 13.3 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Documentation Support
      1. 14.1.1 Related Documentation
    2. 14.2 Related Links
    3. 14.3 接收文档更新通知
    4. 14.4 支持资源
    5. 14.5 Trademarks
    6. 14.6 静电放电警告
    7. 14.7 术语表
  15. 15Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

8.5 Electrical Characteristics

Limits apply over the junction temperature (TJ) range of -40°C to +150°C; VIN = 13.5 V, fSW =400 kHz, CVCC = 2.2 µF, RSNS = 15 mΩ, RIMON = 13 kΩ, RILIMIT= 13 kΩ, RSET= 300 Ω unless otherwise stated. Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (IN PIN)
VIN Operating input voltage range 4.5 36 V
IQ Operating quiescent current (non switching) VEN/UVLO = VIN, CTRL1 = CTRL2 = VCC, VCSN = 8V, CC1 or CC2 = RD, CC2 or CC1 = open 700 990 µA
IQ-SB Standby quiescent current VEN/UVLO = VIN, CTRL1 = CTRL2 = VCC, CC1 and CC2 = open 290 µA
ISD Shutdown quiescent current; measured at IN pin. EN= 0 10 16 µA
ENABLE and UVLO (EN/UVLO PIN)
VEN/UVLO_VCC_H EN/UVLO input level required to turn on internal LDO VEN/UVLO rising threshold 1.14 V
VEN/UVLO_VCC_L EN/UVLO input level required to turn off internal LDO VEN/UVLO falling threshold 0.3 V
VEN/UVLO_H EN/UVLO input level required to turn on state machine VEN/UVLO rising threshold 1.140 1.200 1.260 V
VEN/UVLO_HYS Hysteresis VEN/UVLO falling threshold 90 mV
ILKG_EN/UVLO Enable input leakage current VEN/UVLO = 3.3 V 0.5 uA
INTERNAL LDO
VBOOT_UVLO Bootstrap voltage UVLO threshold 2.2 V
VCC Internal LDO output voltage appearing on VCC pin 6 V ≤ VIN ≤ 36 V 4.75 5 5.25 V
VCC_UVLO_R Rising UVLO threshold 3.4 3.6 3.8 V
VCC_UVLO_HYS Hysteresis 600 mV
CURRENT LIMIT VOLTAGE (CSP - CSN/OUT PINS) TO ACTIVATE BUCK AVG CURRENT LIMITING
(VCSP – VCSN/OUT) Current limit voltage buck regulator control loop VCSN = 5 V, RSET = 300 Ω, RILIMIT = 13 kΩ, RIMON = 13 kΩ, -40°C ≤ TJ ≤ 125°C 43.5 46 48.5 mV
(VCSP – VCSN/OUT) Current limit voltage buck regulator control loop VCSN = 5 V, RSET = 300 Ω, RILIMIT = 13 kΩ, RIMON = 13 kΩ, -40°C ≤ TJ ≤ 150°C 42.5 46 49.5 mV
(VCSP – VCSN/OUT) Current limit voltage buck regulator control loop VCSN = 5 V, RSET = 300 Ω, RILIMIT = 26.1 kΩ, RIMON = 13 kΩ, -40°C ≤ TJ ≤ 125°C 20 22.5 25 mV
(VCSP – VCSN/OUT) Current limit voltage buck regulator control loop VCSN = 5 V, RSET = 300 Ω, RILIMIT = 26.1 kΩ, RIMON = 13 kΩ, -40°C ≤ TJ ≤ 150°C 19 22.5 26 mV
CURRENT LIMIT VOLTAGE (CSP - CSN/OUT PINS) TO ACTIVATE EXTERNAL NFET CURRENT LIMITING
(VCSP – VCSN/OUT) Current limit voltage NFET control loop VCSN = 5 V, RSET = 300 Ω, RILIMIT = 6.8 kΩ, RIMON = 13 kΩ, -40°C ≤ TJ ≤ 125°C 41 44 47 mV
(VCSP – VCSN/OUT) Current limit voltage NFET control loop VCSN = 5 V, RSET = 300 Ω, RILIMIT = 6.8 kΩ, RIMON = 13 kΩ, -40°C ≤ TJ ≤ 150°C 39.5 44 48.5 mV
(VCSP – VCSN/OUT) Current limit voltage NFET control loop VCSN = 5 V, RSET = 300 Ω, RILIMIT = 13.7 kΩ, RIMON = 13 kΩ, -40°C ≤ TJ ≤ 125°C 19 22 25 mV
(VCSP – VCSN/OUT) Current limit voltage NFET control loop VCSN = 5 V, RSET = 300 Ω, RILIMIT = 13.7 kΩ, RIMON = 13 kΩ, -40°C ≤ TJ ≤ 150°C 18 22 26 mV
(VCSP – VCSN/OUT) Secondary current limit voltage NFET control loop VCSN = 5 V, RSET = 300 Ω, RILIMIT = 6.8 kΩ, RIMON = 13 kΩ, -40°C ≤ TJ ≤ 125°C 65.6 70.4 75.2 mV
(VCSP – VCSN/OUT) Secondary current limit voltage NFET control loop VCSN = 5 V, RSET = 300 Ω, RILIMIT = 6.8 kΩ, RIMON = 13 kΩ, -40°C ≤ TJ ≤ 150°C 63.2 70.4 77.6 mV
(VCSP – VCSN/OUT) Secondary current limit voltage NFET control loop VCSN = 5 V, RSET = 300 Ω, RILIMIT = 13.7 kΩ, RIMON = 13 kΩ, -40°C ≤ TJ ≤ 125°C 30.4 35.2 40 mV
(VCSP – VCSN/OUT) Secondary current limit voltage NFET control loop VCSN = 5 V, RSET = 300 Ω, RILIMIT = 13.7 kΩ, RIMON = 13 kΩ, -40°C ≤ TJ ≤ 150°C 28.8 35.2 41.6 mV
CURRENT LIMIT - BUCK REGULATOR PEAK CURRENT LIMIT
IL-SC-HS High-side current limit 6.2 7.1 8.0 A
IL-SC-LS Low-side current limit 4.6 5.4 6.2 A
IL-NEG-LS Low-side negative current limit –3.7 –2.7 –1.7 A
CABLE COMPENSATION VOLTAGE
VIMON Cable compensation voltage (VCSP – VCSN) = 46 mV, RSET = 300 Ω, RILIMIT = 13 kΩ, RIMON = 13 kΩ 0.935 1 1.065 V
VIMON Cable compensation voltage (VCSP – VCSN) = 23 mV, RSET = 300 Ω, RILIMIT = 13 kΩ, RIMON = 13 kΩ 0.435 0.5 0.565 V
VIMON Cable compensation voltage (internal clamp) (VCSP –VCSN) = 46 mV, RSET = 300 Ω, RILIMIT = 13 kΩ, RIMON = open 1.8 V
BUCK OUTPUT VOLTAGE (CSN/OUT PIN)
VCSN/OUT Output voltage CC1 or CC2 pulldown resistance = Rd, RIMON = 0 Ω, RILIMIT = 0 Ω, –40°C ≤ TJ ≤ 125°C 5.05 5.10 5.15 V
VCSN/OUT Output voltage accuracy CC1 or CC2 pulldown resistance = Rd, RIMON = 0 Ω, RILIMIT = 0 Ω –1 1 %
VCSN/OUT_OV Overvoltage level on CSN/OUT pin which buck regulator stops switching VCSN/OUT rising 7.1 7.5 7.9 V
VCSN/OUT_OV_HYS Hysteresis 500 mV
VHC CSN / OUT pin voltage required to trigger short circuit hiccup mode 2 V
VDROP Dropout voltage ( VIN-VOUT ) VIN = VOUT + VDROP, VOUT = 5.1V, IOUT = 3A 150 mV
BUCK REGULATOR INTERNAL RESISTANCE
RDS-ON-HS High-side MOSFET ON-resistance Load = 3 A, TJ = 25°C 40 45 mΩ
RDS-ON-HS High-side MOSFET ON-resistance Load = 3 A, -40°C ≤ TJ ≤ 125°C 40 68 mΩ
RDS-ON-HS High-side MOSFET ON-resistance Load = 3 A, -40°C ≤ TJ ≤ 150°C 40 75 mΩ
RDS-ON-LS Low-side MOSFET ON-resistance Load = 3 A, TJ = 25C 35 41 mΩ
RDS-ON-LS Low-side MOSFET ON-resistance Load = 3 A, -40°C ≤ TJ ≤ 125°C 35 60 mΩ
RDS-ON-LS Low-side MOSFET ON-resistance Load = 3 A, -40°C ≤ TJ ≤ 150°C 35 68 mΩ
NFET GATE DRIVE (LS_GD PIN)
VLS_GD NFET gate drive output voltage VCSN/OUT = 5.1 V, CG = 1000 pF 9.5 11 12.5 V
ILS_DR_SRC NFET gate drive output source current VCSN/OUT = 5.1 V, CG = 1000 pF 2 3 4 µA
ILS_DR_SNK NFET gate drive output sink current VCSN/OUT = 5.1 V, CG = 1000 pF 20 35 50 µA
VLS_GD_UVLO_R VCSN/OUT rising threshold for LS_GD operation VCSN/OUT rising 2.85 3 3.18 V
VLS_GD_UVLO_HYS Hysteresis 80 mV
BUS DISCHARGE (BUS PIN)
RBUS_DCHG BUS discharge resistance VBUS = 4 V 250 320 550 Ω
VBUS_NO_DCHG Falling threshold for VBUS not discharged  0.8 V
RBUS_DCHG_BLEED BUS bleed resistance VBUS = 4 V, No sink termination on CC lines, Time > tW_BUS_DCHG 100 130 200 kΩ
VBUS_OV Rising threshold for BUS pin overvoltage protection VBUS rising 6.6 7 7.3 V
VBUS_OV_HYS Hysteresis 180 mV
RBUS_DCHG_18V Discharge resistance for BUS VBUS = 18V, measure leakage current 29 kΩ
RBUS_DCHG_8V Discharge resistance for BUS VBUS = 8V, measure leakage current 35 kΩ
CC1 AND CC2 - VCONN POWER SWITCH (CC1 AND CC2 PINS)
RDS-ON On-state resistance ICCn = 250 mA, TJ = 25°C 500 540 mΩ
RDS-ON On-state resistance ICCn = 250 mA, –40°C ≤ TJ ≤ 125°C 500 830 mΩ
RDS-ON On-state resistance ICCn = 250 mA, –40°C ≤ TJ ≤ 150°C, 500 920 mΩ
IOS_CCn VCONN short circuit current limit Short circuit current limit 350 430 550 mA
RVCONN_DCHG Discharge resistance CC pin that was providing VCONN before detach: VCCX = 4V 650 850 1100 Ω
VTH Falling threshold for discharged CC pin that was providing VCONN before detach 570 600 630 mV
VTH Discharged threshold hysteresis 100 mV
VCCx_OV Rising threshold for CCn pin overvoltage protection CC pin voltage VCCn rising 5.8 6.1 6.4 V
VCCx_OV_HYS Hysteresis 150 mV
RCCn_DCHG_18V Discharge resistance for CCn CC pin voltage VCCn = 18V, measure leakage current 40 kΩ
RCCn_DCHG_8V Discharge resistance for CCn CC pin voltage VCCn = 8V, measure leakage current 86 kΩ
CC1/CC2 CONNECT MANAGEMENT: DANGLING ELECTRONICALLY MARKED CABLE MODE
ISRC_CCn Sourcing current on the passthrough CC line CC pin voltage 0 V ≤ VCCn ≤ 1.5 V 64 80 96 µA
ISRC_CCn Sourcing current on the Ra CC line CC pin voltage 0 V ≤ VCCn ≤ 1.5 V 64 80 96 µA
CC1/CC2 CONNECT MANAGEMENT: UFP MODE
ISRC_CCn Sourcing current VCTRL1 = VCC and VCTRL2 = VCC, CC pin voltage: 0 V ≤ VCCn ≤ 1.5 V (with CDP mode) 308 330 354 µA
ISRC_CCn Sourcing current VCTRL1 = VCC and VCTRL2 = GND, CC pin voltage: 0 V ≤ VCCn ≤ 1.5 V (with SDP mode) 168 180 192 µA
ISRC_CCn Sourcing current VCTRL1 = GND and VCTRL2 = VCC, CC pin voltage: 0 V ≤ VCCn ≤ 1.5 V (client mode) 168 180 192 µA
ISRC_CCn Sourcing current VCTRL1 = GND and VCTRL2 = GND, CC pin voltage: 0 V ≤ VCCn ≤ 1.5 V (client mode) 168 180 192 µA
IREV Reverse leakage current CCx is the CC pin under test, CCy is the other CC pin. CC pin voltage VCCx = 5.5 V, CCy = 0V or floating, VEN = 0 V, IREV is current into CCx pin 0 5 µA
IREV Reverse leakage current CCx is the CC pin under test, CCy is the other CC pin. CC pin voltage VCCx = 5.5 V, CCy = 0, VEN = VIN, IREV is current into CCx pin under test 9 12 µA
FAULT, LD_DET, POL
VOL FAULT Output low voltage ISNK_PIN = 0.5 mA 250 mV
IOFF FAULT Off-state leakage VPIN = 5.5 V 1 µA
VOL LD_DET, POL Output low voltage ISNK_PIN = 0.5 mA 250 mV
IOFF LD_DET, POL Off-state leakage VPIN = 5.5 V 1 µA
CTRL1, CTRL2 - LOGIC INPUTS
VIH Rising threshold voltage 1.48 2 V
VIL Falling threshold voltage 0.85 1.30 V
VHYS Hysteresis 180 mV
IIN Input current –1 1 µA
DP_IN AND DM_IN OVERVOLTAGE PROTECTION
VDx_IN_OV Rising threshold for Dx_IN overvoltage protection DP_IN or DM_IN rising 3.7 3.9 4.15 V
Hysteresis 100 mV
RDx_IN_DCHG_18V Discharge resistance for Dx_IN VDx_IN = 18V, measure leakage current 94 kΩ
RDx_IN_DCHG_5V Discharge resistance for Dx_IN VDx_IN = 5V, measure leakage current 416 kΩ
HIGH-BANDWIDTH ANALOG SWITCH
RDS_ON DP and DM switch on-resistance VDP_OUT = VDM_OUT = 0 V, IDP_IN = IDM_IN = 30 mA 3.4 6.3 Ω
RDS_ON DP and DM switch on-resistance VDP_OUT = VDM_OUT = 2.4 V, IDP_IN = IDM_IN = –15 mA 4.3 7.7 Ω
|ΔRDS_ON| Switch resistance mismatch between DP and DM channels VDP_OUT = VDM_OUT = 0 V, IDP_IN = IDM_IN = 30 mA 0.05 0.15 Ω
|ΔRDS_ON| Switch resistance mismatch between DP and DM channels VDP_OUT = VDM_OUT = 2.4 V, IDP_IN = IDM_IN = –15 mA 0.05 0.15 Ω
CIO_OFF DP/DM switch off-state capacitance VEN = 0 V, VDP_IN = VDM_IN = 0.3 V, Vac = 0.03 VPP , f = 1 MHz 6.7 pF
CIO_ON DP/DM switch on-state capacitance VDP_IN = VDM_IN = 0.3 V, Vac = 0.03 VPP, f = 1 MHz 10 pF
OIRR Off-state isolation VEN = 0 V, f = 250 MHz 9 dB
XTALK On-state cross-channel isolation f = 250 MHz 29 dB
Ilkg(OFF) Off-state leakage current, DP_OUT and DM_OUT VEN = 0 V, VDP_IN = V DM_IN = 3.6 V, VDP_OUT = VDM_OUT = 0 V, measure IDP_OUT and IDM_OUT 0.1 1.5 µA
BW Bandwidth (–3 dB) RL = 50 Ω 800 MHz
CHARGING DOWNSTREAM PORT (CDP) DETECT
VDM_SRC DM_IN CDP output voltage VDP_IN = 0.6 V, –250 µA < IDM_IN < 0 µA 0.5 0.6 0.7 V
VDAT_REF DP_IN rising lower window threshold for VDM_SRC activation 0.36 0.38 0.4 V
VDAT_REF Hysteresis 50 mV
VLGC_SRC DP_IN rising upper window threshold for VDM_SRC deactivation 0.91 0.95 0.99 V
VLGC_SRC_HYS Hysteresis 100 mV
IDP_SINK DP_IN sink current VDP_IN = 0.6 V 40 70 100 µA
RT/SYNC THRESHOLD (RT/SYNC PIN)
VIH_RT/SYNC RT/SYNC high threshold for external clock synchronization Amplitude of SYNC clock AC signal (measured at SYNC pin) 2 V
VIL_RT/SYNC RT/SYNC low threshold for external clock synchronization Amplitude of SYNC clock AC signal (measured at SYNC pin) 0.8 V
THERMAL SHUTDOWN
TSD Thermal shutdown Shutdown threshold 160 °C
Recovery threshold 140 °C
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