ZHCSK24D July   2019  – July 2021 TPS25832-Q1 , TPS25833-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 说明（续）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Switching Characteristics
    8. 8.8 Typical Characteristics
  9. 9 Parameter Measurement Information
    1.     18
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Buck Regulator
      2. 10.3.2  Enable/UVLO and Start-up
      3. 10.3.3  RT/SYNC
      4. 10.3.4  Spread-Spectrum Operation
      5. 10.3.5  VCC, VCC_UVLO
      6. 10.3.6  Minimum ON-time, Minimum OFF-time
      7. 10.3.7  Internal Compensation
      8. 10.3.8  Bootstrap Voltage (BOOT)
      9. 10.3.9  RSNS, RSET, RILIMIT, and RIMON
      10. 10.3.10 Overcurrent and Short Circuit Protection
        1. 10.3.10.1 Current Limit Setting using RILIMIT
        2. 10.3.10.2 Buck Average Current Limit Design Example
        3. 10.3.10.3 External MOSFET Gate Drivers
        4. 10.3.10.4 Cycle-by-Cycle Buck Current Limit
      11. 10.3.11 IEC and Overvoltage Protection
        1. 10.3.11.1 VBUS and VCSN/OUT Overvoltage Protection
        2. 10.3.11.2 DP_IN and DM_IN Protection
        3. 10.3.11.3 CC IEC and Overvoltage Protection
      12. 10.3.12 Cable Compensation
        1. 10.3.12.1 Cable Compensation Design Example
      13. 10.3.13 USB Port Control
      14. 10.3.14 FAULT Response
      15. 10.3.15 USB Specification Overview
      16. 10.3.16 USB Type-C® Basics
        1. 10.3.16.1 Configuration Channel
        2. 10.3.16.2 Detecting a Connection
        3. 10.3.16.3 Configuration Channel Pins CC1 and CC2
        4. 10.3.16.4 Current Capability Advertisement and VCONN Overload Protection
        5. 10.3.16.5 Plug Polarity Detection
      17. 10.3.17 Device Power Pins (IN, CSN/OUT, and PGND)
      18. 10.3.18 Thermal Shutdown
      19. 10.3.19 Power Wake
      20. 10.3.20 Thermal Sensing with NTC (TPS25833-Q1)
    4. 10.4 Device Functional Modes
      1. 10.4.1 Shutdown Mode
      2. 10.4.2 Standby Mode
      3. 10.4.3 Active Mode
      4. 10.4.4 Device Truth Table (TT)
      5. 10.4.5 USB Port Operating Modes
        1. 10.4.5.1 USB Type-C® Mode
        2. 10.4.5.2 Standard Downstream Port (SDP) Mode — USB 2.0, USB 3.0, and USB 3.1
        3. 10.4.5.3 Charging Downstream Port (CDP) Mode
        4. 10.4.5.4 Dedicated Charging Port (DCP) Mode (TPS25833-Q1 Only)
          1. 10.4.5.4.1 DCP BC1.2 and YD/T 1591-2009
          2. 10.4.5.4.2 DCP Divider-Charging Scheme
          3. 10.4.5.4.3 DCP 1.2-V Charging Scheme
        5. 10.4.5.5 DCP Auto Mode (TPS25833-Q1 Only)
      6. 10.4.6 High-Bandwidth Data-Line Switches (TPS25832-Q1 Only)
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1  Output Voltage
        2. 11.2.2.2  Switching Frequency
        3. 11.2.2.3  Inductor Selection
        4. 11.2.2.4  Output Capacitor Selection
        5. 11.2.2.5  Input Capacitor Selection
        6. 11.2.2.6  Bootstrap Capacitor Selection
        7. 11.2.2.7  VCC Capacitor Selection
        8. 11.2.2.8  Enable and Under Voltage Lockout Set-Point
        9. 11.2.2.9  Current Limit Set-Point
        10. 11.2.2.10 Cable Compensation Set-Point
        11. 11.2.2.11 LD_DET, POL, and FAULT Resistor Selection
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Ground Plane and Thermal Considerations
    3. 13.3 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 接收文档更新通知
    2. 14.2 支持资源
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 术语表
  15. 15Mechanical, Packaging, and Orderable Information

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8.7 Switching Characteristics

Limits apply over the junction temperature (TJ) range of -40°C to +150°C; VIN = 13.5 V, fSW =400 kHz, CVCC = 2.2 µF, RSNS = 15 mΩ, RIMON = 13 kΩ, RILIMIT= 13 kΩ, RSET= 300 Ω unless otherwise stated. Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
SOFT START
TSSInternal soft-start timeThe time of internal reference to increase from 0 V to 1.0 V357ms
HICCUP MODE
NOCNumber of cycles that LS current limit is tripped to enter Hiccup mode128Cycles
TOCHiccup retry delay time118ms
SW (SW PIN)
TON_MINMinimum turnon-time105ns
TON_MAXMaximum turnon-time, HS timeout in dropout7.5µs
TOFF_MINMinimum turnoff time80ns
DmaxMaximum switch duty cycle98%
TIMING RESISTOR AND INTERNAL CLOCK
fSW_RANGESwitching frequency range using RT mode3002300kHz
fSWSwitching frequencyRT = 49.9 kΩ360400440kHz
Switching frequencyRT = 8.87 kΩ195321002247kHz
FSSSFrequency span of spread spectrum operation±6%
BUS DISCHARGE
tDEGA_OUT_DCHGDischarge asserting deglitch5.012.523.4ms
tW_BUS_DCHGVBUS discharge time after sink termination removed from CC linesVBUS = 1 V, time ISNK_OUT > 1 mA after sink termination removed from CC lines150266400ms
CC1/CC2 - VCONN POWER SWITCH 5.1 kΩ on one CC pin and 1 kΩ on the other
trOutput voltage rise timeCL = 1 µF, RL = 100 Ω (measured from 10% to 90% of final value)0.781.11.95ms
tfOutput voltage fall time0.180.320.37
tonOutput voltage turnon-timeCL = 1 µF, RL = 100 Ω4.16.28.5ms
toffOutput voltage turnoff time0.511.6
CC1/CC2 VCONN POWER SWITCH: CURRENT LIMIT
tIOSShort circuit response time15µs
CC1/CC2 - CONNECT MANAGEMENT - ATTACH AND DETACH DEGLITCH
tDEGA_CC_ATTAttach asserting deglitch1.12.083.29ms
tDEGD_CC_DETDetach asserting deglitch for exiting UFP state6.9812.719.4ms
CC1/CC2 - CONNECT MANAGEMENT - ATTACHED MODE 5.1-kΩ or 1-kΩ termination on at least one CC pin
tDEGA_CC_SHORTDetach, Rd and Ra asserting deglitch78195366µs
tDEGA_CC_LONGLong deglitch87150217ms
CC1/CC2 - CONNECT MANAGEMENT - VCONN DISCHARGED MODE
tW_CC_DCHGDischarge wait time376699ms
NFET DRIVER
trVLS_DR rise timeVOUT = 5.1 V, NFET = CSD87502Q2, time from LS_GD 10% to 90%1000µs
tfVLS_DR fall timeVOUT = 5.1 V, NFET = CSD87502Q2, time from LS_GD time 90% to 10%100µs
CURRENT LIMIT - EXTERNAL NFET CONNECTED BETWEEN CSN/OUT AND BUS, LS_GD CONNECTED TO FET GATE
tOC_HIC_ONON-time during hiccup mode2ms
tOC_HIC_OFFOFF-time during hiccup mode263ms
FAULT DUE TO VBUS OC, VBUS OV, DP OV, DM OV, CC OV, CC OC
tDEGLAAsserting deglitch time5.58.211.5ms
tDEGLDDe-asserting deglitch time5.58.211.5ms
LD_DET, POL
tDEGLAAsserting deglitch time88150220ms
tDEGLDDe-asserting deglitch time7.012.719.4ms
THERM_WARN (TPS25833-Q1)
tDEGLAAsserting deglitch time0ms
tDEGLDDe-asserting deglitch time0ms
HIGH-BANDWIDTH ANALOG SWITCH (TPS25832-Q1)
tpdAnalog switch propagation delay0.14ns
tSKAnalog switch skew between opposite transitions of the same port (tPHL – tPLH)0.02ns
tOV_DnDP_IN and DM_IN overvoltage protection response time2µs
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