米6体育平台手机版

ZHCSE39A August 2015 – August 2015

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

DRC|10
- MPDS117L

散热焊盘机械数据 (封装 | 引脚)

DRC|10
- QFND013N

订购信息

8 Detailed Description

8.1 Overview

The TPS25923x is an e-fuse with integrated power switch that is used to manage current/voltage/start-up voltage ramp to a connected load. The device starts its operation by monitoring the VIN bus. When VIN exceeds the undervoltage-lockout threshold (VUVR), the device samples the EN/UVLO pin. A high level on this pin enables the internal MOSFET. As VIN rises, the internal MOSFET of the device will start conducting and allow current to flow from VIN to OUT. When EN/UVLO is held low (below VENF), internal MOSFET is turned off. User also has the ability to modify the output voltage ramp time by connecting a capacitor between dV/dT pin and GND.

After a successful start-up sequence, the device now actively monitors its load current and input voltage, ensuring that the adjustable overload current limit I_OL is not exceeded and input voltage spikes are safely clamped to V_OVC level at the output. This keeps the output device safe from harmful voltage and current transients. The device also has built-in thermal sensor. In the event device temperature (T_J) exceeds T_SHDN, typically 150°C, the thermal shutdown circuitry will shut down the internal MOSFET thereby disconnecting the load from the supply. In TPS259230, the output will remain disconnected (MOSFET open) until power to device is recycled or EN/UVLO is toggled (pulled low and then high). The TPS259231 device will remain off during a cooling period until device temperature falls below T_SHDN – 10°C, after which it will attempt to restart. This ON and OFF cycle will continue until fault is cleared.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 GND

This is the most negative voltage in the circuit and is used as a reference for all voltage measurements unless otherwise specified.

8.3.2 VIN

Input voltage to the TPS25923x. A ceramic bypass capacitor close to the device from VIN to GND is recommended to alleviate bus transients. The recommended operating voltage range is 4.5 V to 5.5 V for TPS25923x. The device can continuously sustain a voltage of 20 V on VIN pin. However, above the recommended maximum bus voltage, the device will be in over-voltage protection (OVP) mode, limiting the output voltage to V_OVC. The power dissipation in OVP mode is P_{D_OVP} = (V_VIN - V_OVC) x I_OUT, which can potentially heat up the device and cause thermal shutdown.

8.3.3 dV/dT

Connect a capacitor from this pin to GND to control the slew rate of the output voltage at power-on. This pin can be left floating to obtain a predetermined slew rate (minimum T_dVdT) on the output. Equation governing slew rate at start-up is shown below:

Equation 1. TPS259230 TPS259231 eq1_X_lvsc11.gif

Where:

I_dVdT = 220 nA (TYP)
C_INT = 70 pF (TYP)
GAIN_dVdT = 4.85

The total ramp time (T_dVdT) for 0 to VIN can be calculated using the following equation:

Equation 2. TPS259230 TPS259231 eq2_X_lvsc11.gif

For details on how to select an appropriate charging time/rate, refer to the applications section Setting Output Voltage Ramp Time (TdVdT).

8.3.4 BFET

Connect this pin to an external NFET that can be used to disconnect input supply from rest of the system in the event of power failure at VIN. The BFET pin is controlled by either input UVLO (V_UVR) event or EN/UVLO (see Table 1). BFET can source charging current of 2 µA (TYP) and sink (discharge) current from the gate of the external FET via a 26-Ω internal discharge resistor to initiate fast turn-off, typically <1 µs. Due to 2 µA charging current, it is recommended to use >10 MΩ impedance when probing the BFET node.

Table 1. BFET

EN/UVLO > V_ENR	VIN > V_UVR	BFET MODE
H	H	Charge
X	L	Discharge
L	X	Discharge

8.3.5 EN/UVLO

As an input pin, it controls both the ON/OFF state of the internal MOSFET and that of the external blocking FET. In its high state, the internal MOSFET is enabled and charging begins for the gate of external FET. A low on this pin will turn off the internal MOSFET and pull the gate of the external FET to GND via the built-in discharge resistor. High and Low levels are specified in the parametric table of the datasheet. The EN/UVLO pin is also used to clear a thermal shutdown latch in the TPS259230 by toggling this pin (H→L).

The internal de-glitch delay on EN/UVLO falling edge is intentionally kept low (1 us typical) for quick detection of power failure. When used with a resistor divider from supply to EN/UVLO to GND, power-fail detection on EN/UVLO helps in quick turn-off of the BFET driver, thereby stopping the flow of reverse current (see typical application diagram, Figure 43). For applications where a higher de-glitch delay on EN/UVLO is desired, or when the supply is particularly noisy, it is recommended to use an external bypass capacitor from EN/UVLO to GND.

8.3.6 ILIM

The device continuously monitors the load current and keeps it limited to the value programmed by R_ILIM. After start-up event and during normal operation, current limit is set to I_OL (over-load current limit).

Equation 3. TPS259230 TPS259231 EQ3_IOL_lvsc11.gif

When power dissipation in the internal MOSFET [P_D = (V_VIN – V_OUT) × I_OUT] exceeds 10 W, there is a 2% – 12% thermal foldback in the current limit value so that I_OL drops to I_SC. In each of the two modes, MOSFET gate voltage is regulated to throttle short-circuit and overload current flowing to the load. Eventually, the device shuts down due to over temperature.

TPS259230 TPS259231 AI_foldback_lvsc11.gif

Figure 36. Thermal Foldback in Current Limit

During a transient short circuit event, the current through the device increases very rapidly. The current-limit amplifier cannot respond very quickly to this event due to its limited bandwidth. Therefore, the TPS2592 incorporates a fast-trip comparator, which shuts down the pass device very quickly when I_OUT > I_FASTRIP, and terminates the rapid short-circuit peak current. The trip threshold is set to 60% higher than the programmed over-load current limit (I_FASTRIP = 1.6 x I_OL). After the transient short-circuit peak current has been terminated by the fast-trip comparator, the current limit amplifier smoothly regulates the output current to I_OL(see figure below).

Figure 37. Fast-Trip Current

TPS259230 TPS259231 FP_Fig_26_37_slvscv0.png

Figure 38. Fast-Trip and Current Limit Amplifier Response for Short Circuit

8.4 Device Functional Modes

The TPS25923x is a hot-swap controller with integrated power switch that is used to manage current/voltage/start-up voltage ramp to a connected load. The device starts its operation by monitoring the VIN bus. When V_VIN exceeds the undervoltage-lockout threshold (V_UVR), the device samples the EN/UVLO pin. A high level on this pin enables the internal MOSFET and also start charging the gate of external blocking FET (if connected) via the BFET pin. As VIN rises, the internal MOSFET of the device and external FET (if connected) will start conducting and allow current to flow from VIN to OUT. When EN/UVLO is held low (that is, below V_ENF), the internal MOSFET is turned off and BFET pin is discharged, thereby, blocking the flow of current from VIN to OUT. User also has the ability to modify the output voltage ramp time by connecting a capacitor between dV/dT pin and GND.

Having successfully completed its start-up sequence, the device now actively monitors its load current and input voltage, ensuring that the adjustable overload current limit I_OL is not exceeded and input voltage spikes are safely clamped to V_OVC level at the output. This keeps the output device safe from harmful voltage and current transients. The device also has built-in thermal sensor. In the event device temperature (T_J) exceeds T_SHDN , typically 150°C, the thermal shutdown circuitry will shut down the internal MOSFET thereby disconnecting the load from the supply. In the TPS259230, the output will remain disconnected (MOSFET open) until power to device is recycled or EN/UVLO is toggled (pulled low and then high). The TPS259231 device will remain off during a cooling period until device temperature falls below T_SHDN – 10°C, after which it will attempt to restart. This ON and OFF cycle will continue until fault is cleared.