Table 1. Design Parameters

9.2.1.2.1 Step by Step Design Procedure

To begin the design process a few parameters must be decided upon. The designer needs to know the following:

• Normal input operation voltage
• Maximum output capacitance
• Maximum current Limit
• Load during start-up
• Maximum ambient temperature of operation

This design procedure below seeks to control the junction temperature of device under both static and transient conditions by proper selection of output ramp-up time and associated support components. The designer can adjust this procedure to fit the application and design criteria.

9.2.1.2.2 Programming the Current-Limit Threshold: R_ILIM Selection

The R_ILIM resistor at the ILIM pin sets the over load current limit, this can be set using Equation 4.

Equation 4.

For ILIM = 3.7 A, from Equation 4, R_ILIM is 100 kΩ, choose closest standard value resistor with 1% tolerance.

9.2.1.2.3 Undervoltage Lockout Set Point

The undervoltage lockout (UVLO) trip point is adjusted using the external voltage divider network of R₁ and R₂ as connected between IN, EN/UVLO and GND pins of the device. The values required for setting the undervoltage are calculated solving Equation 5.

Equation 5.

Where V_ENR is enable voltage rising threshold (1.4 V). Since R1 and R2 will leak the current from input supply (Vin), these resistors should be selected based on the acceptable leakage current from input power supply (Vin).

The current drawn by R1 and R2 from the power supply {I_(R12) = V_(IN)/(R₁ + R₂)}.

However, leakage currents due to external active components connected to the resistor string can add error to these calculations. So, the resistor string current, I_(R12) must be chosen to be 20x greater than the leakage current expected.

For default UVLO of V_UVR = 4.3 V, select R2 = OPEN, and R₁ = 1 MΩ. Since EN/UVLO pin is rated only to 7 V, it cannot be connected directly to VIN = 12 V. It has to be connected through R₁ = 1 MΩ only, so that the pull-up current for EN/UVLO pin is limited to < 20 µA.

The power failure threshold is detected on the falling edge of supply. This threshold voltage is 4% lower than the rising threshold, V_UVR. This is calculated using Equation 6.

Where V_UVR is 4.3 V, Power fail threshold set is : 4.1 V.

9.2.1.2.4 Setting Output Voltage Ramp Time (T_dVdT)

For a successful design, the junction temperature of device should be kept below the absolute-maximum rating during both dynamic (start-up) and steady state conditions. Dynamic power stresses often are an order of magnitude greater than the static stresses, so it is important to determine the right start-up time and in-rush current limit required with system capacitance to avoid thermal shutdown during start-up with and without load.

The ramp-up capacitor C_dVdT needed is calculated considering the two possible cases.

9.2.1.2.4.1 Case 1: Start-Up without Load: Only Output Capacitance C_OUT Draws Current During Start-Up

During start-up, as the output capacitor charges, the voltage difference as well as the power dissipated across the internal FET decreases. The average power dissipated in the device during start-up is calculated using Equation 8.

For TPS25926x device, the inrush current is determined as,

Equation 7.

Power dissipation during start-up is:

Equation 8.

Equation 8 assumes that load does not draw any current until the output voltage has reached its final value.

9.2.1.2.4.2 Case 2: Start-Up with Load: Output Capacitance C_OUT and Load Draws Current During Start-Up

When load draws current during the turn-on sequence, there will be additional power dissipated. Considering a resistive load during start-up (R_L(SU)), load current ramps up proportionally with increase in output voltage during T_dVdT time. The average power dissipation in the internal FET during charging time due to resistive load is given by:

Equation 9.

Total power dissipated in the device during startup is:

Equation 10.

Total current during startup is given by:

Equation 11.

If I_(STARTUP) > I_OL, the device limits the current to I_OL and the current limited charging time is determined by:

Equation 12.

The power dissipation, with and without load, for selected start-up time should not exceed the shutdown limits as shown in Figure 43:

Figure 43. Thermal Shutdown Limit Plot

For the design example under discussion, select ramp-up capacitor C_dVdT = OPEN. Then, using Equation 2:

Equation 13.

The inrush current drawn by the load capacitance (C_OUT) during ramp-up using Equation 14:

Equation 14.

The inrush power dissipation is calculated using Equation 15:

Equation 15.

For 90 mW of power loss, the thermal shut down time of the device should not be less than the ramp-up time T_dVdT to avoid the false trip at maximum operating temperature. From thermal shutdown limit graph Figure 43 at T_A = 85°C, for 90 mW of power, the shutdown time is infinite. So it is safe to use 0.79 ms as start-up time without any load on output.

Considering the start-up with load 4 Ω, the additional power dissipation, when load is present during start up is calculated using Equation 9:

Equation 16.

The total device power dissipation during start up is:

Equation 17.

From thermal shutdown limit graph at T_A = 85°C, the thermal shutdown time for 6.09 W is more than 10 ms. So it is well within acceptable limits to use no external capacitor (C_dV/dT) with start-up load of 4 Ω.

If, due to large C_OUT, there is a need to decrease the power loss during start-up, it can be done with increase of C_dVdT capacitor.

9.2.1.2.5 Support Component Selection - C_VIN

C_VIN is a bypass capacitor to help control transient voltages, unit emissions, and local supply noise. Where acceptable, a value in the range of 0.001 μF to 0.1 μF is recommended for C_VIN.