ZHCSCK2 June 2014
PRODUCTION DATA.
- 1 特性
- 2 应用范围
- 3 说明
- 4 简化电路原理图
- 5 修订历史记录
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Parametric Measurement Information
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3
Feature Description
- 9.3.1 Enable and Adjusting Undervoltage Lockout
- 9.3.2 Overvoltage Protection (OVP)
- 9.3.3 Hot Plug-in and In-Rush Current Control
- 9.3.4 Overload and Short Circuit Protection :
- 9.3.5 FAULT Response
- 9.3.6 Current Monitoring:
- 9.3.7 Power Good Comparator
- 9.3.8 IN, OUT and GND Pins
- 9.3.9 Thermal Shutdown:
- 9.4 Device Functional Modes
-
10Application and Implementation
- 10.1 Application Information
- 10.2
Typical Application
- 10.2.1
eFuse for Enterprise SSDs
- 10.2.1.1 Design Requirements
- 10.2.1.2
Detailed Design Procedure
- 10.2.1.2.1 Step by Step Design Procedure
- 10.2.1.2.2 Programming the Current-Limit Threshold: R(ILIM) Selection
- 10.2.1.2.3 Undervoltage Lockout and Overvoltage Set Point
- 10.2.1.2.4 Programming Current Monitoring Resistor - RIMON
- 10.2.1.2.5 Setting Output Voltage Ramp time (tdVdT)
- 10.2.1.2.6 Programing the Power Good Set Point
- 10.2.1.2.7 Support Component Selections - R6, R7 and CIN
- 10.2.1.3 Application Curves
- 10.2.1
eFuse for Enterprise SSDs
- 10.3 System Examples
- 11Power Supply Recommendations
- 12Layout
- 13器件和文档支持
- 14机械封装和可订购信息
9 Detailed Description
9.1 Overview
TPS25940 is a smart eFuse with integrated back-to-back FETs and enhanced built-in protection circuitry. It provides robust protection for all systems and applications powered from 2.7 V to 18 V.
For hot-plug-in boards, the device provides hot-swap power management with in-rush current control and programmable output ramp-rate. The device integrates overcurrent and short circuit protection. The precision overcurrent limit helps to minimize over design of the input power supply, while the fast response short circuit protection immediately isolates the load from input when a short circuit is detected. The device allows the user to program the overcurrent limit threshold between 0.6 A and 5.3 A via an external resistor.
The device provides precise monitoring of voltage bus for brown-out and overvoltage conditions and asserts fault for downstream system. Its overall threshold accuracy of 2% ensures tight supervision of bus, eliminating the need for a separate supply voltage supervisor chip.
The device is designed to protect systems such as enterprise SSD drives against sudden power loss events. The device monitors V(IN) and V(OUT) to provide true reverse blocking from output when reverse condition or input power fail condition is detected. Also, the device signals the downstream controller to initiate transfer of power to the hold-up capacitor for data hardening.
The additional features include:
- Precise current monitor output for health monitoring of the system
- Additional power good comparator with precision internal reference for output or any other rail voltage monitoring
- Over temperature protection to safely shutdown in the event of an overcurrent event
- De-glitched fault reporting for brown-out and overvoltage faults
- A choice of latched or automatic restart mode
9.2 Functional Block Diagram
Figure 43. TPS25940A/L Block Diagram
9.3 Feature Description
9.3.1 Enable and Adjusting Undervoltage Lockout
The EN/UVLO pin controls the ON/OFF state of the internal FET. A voltage V(EN/UVLO) < V(ENF) on this pin will turn off the internal FET, thus disconnecting IN from OUT, while voltage below V(SHUTF) will take the device into shutdown mode, with IQ less than 15 µA to ensure minimal power loss. Cycling EN/UVLO low and then back high resets the TPS25940L that has latched off due to a fault condition.
The internal de-glitch delay on EN/UVLO falling edge is kept low for quick detection of power failure. For applications where a higher de-glitch delay on EN/UVLO is desired, or when the supply is particularly noisy, it is recommended to use an external bypass capacitor from EN/UVLO terminal to GND.
The undervoltage lock out can be programmed by using an external resistor divider from supply IN terminal to EN/UVLO terminal to GND as shown in Figure 44. When an undervoltage or input power fail event is detected, the internal FET is quickly turned off, and FLT is asserted. If the Under-Voltage Lock-Out function is not needed, the EN/UVLO terminal should be connected to the IN terminal. EN/UVLO terminal should not be left floating.
The device also implements internal undervoltage-lockout (UVLO) circuitry on the IN terminal. The device disables when the IN terminal voltage falls below internal UVLO Threshold V(UVF). The internal UVLO threshold has a hysteresis of 115mV.
Figure 44. UVLO and OVP Thresholds Set By R1, R2 and R3
9.3.2 Overvoltage Protection (OVP)
The device incorporates circuit to protect system during overvoltage conditions. A resistor divider connected from the supply to OVP terminal to GND (as shown in Figure 44) programs the overvoltage threshold. A voltage more than V(OVPR) on OVP pin turns off the internal FET and protects the downstream load. This pin should be tied to GND when not used.
9.3.3 Hot Plug-in and In-Rush Current Control
The device is designed to control the in-rush current upon insertion of a card into a live backplane or other "hot" power source. This limits the voltage sag on the backplane’s supply voltage and prevents unintended resets of the system power. A slew rate controlled startup (dVdT) also helps to eliminate conductive and radiative interferences. An external capacitor connected from the dVdT pin to GND defines the slew rate of the output voltage at power-on (as shown in Figure 45). Equation governing slew rate at start-up is shown in Equation 1 :
Figure 45. Output Ramp Up Time tdVdT is Set by C(dVdT)
Where:
- I(dVdT) = 1 µA (typical)
-
= Desired output slew rate - GAIN(dVdT) = dVdT to OUT gain = 12
The total ramp time (tdVdT) of V(OUT) for 0 to V(IN) can be calculated using Equation 2:
The inrush current, I(INRUSH) can be calculated as
The dVdT pin can be left floating to obtain a predetermined slew rate (tdVdT) on the output. When terminal is left floating, the device sets an internal ramp rate of 12V/ms for output (V(OUT)) ramp.
Figure 58 and Figure 59 illustrate the inrush current control behavior of the device. For systems where load is present during start-up, the current never exceeds the overcurrent limit set by R(ILIM) resistor for the application. For defining appropriate charging time/rate under different load conditions, refer to the Setting Output Voltage Ramp time (tdVdT) section.
9.3.4 Overload and Short Circuit Protection :
At all times load current is monitored by sensing voltage across an internal sense resistor. During overload events, current is limited to the current limit (I(LIM)) programmed by R(ILIM) resistor
- I(LIM) is overload current limit in Ampere
- R(ILIM) is the current limit resistor in kΩ
The device incorporates two distinct levels: a current limit (I(LIM)) and a fast-trip threshold (I(FASTRIP)). Fast trip and current limit operation are shown in Figure 46.
Bias current on ILIM pin directly controls current-limiting behavior of the device, and PCB routing of this node must be kept away from any noisy (switching) signals.
9.3.4.1 Overload Protection
For overload conditions, the internal current-limit amplifier regulates the output current to I(LIM). The output voltage droops during the current regulation, resulting in increased power dissipation in the device. If the device junction temperature reaches the thermal shutdown threshold (T(TSD)), the internal FET is turned off. Once in thermal shutdown, The TPS25940L version stays latched off, whereas TPS25940A commences an auto-retry cycle 128 ms after TJ < [T(TSD) - 12°C]. During thermal shutdown, the fault pin FLT pulls low to signal a fault condition. Figure 62 and Figure 63 illustrate overload behavior.
9.3.4.2 Short Circuit Protection
During a transient short circuit event, the current through the device increases very rapidly. As current-limit amplifier cannot respond quickly to this event due to its limited bandwidth, the device incorporates a fast-trip comparator, with a threshold I(FASTRIP). This comparator shuts down the pass device within 1µs, when the current through internal FET exceeds I(FASTRIP) (I(OUT) > I(FASTRIP)), and terminates the rapid short-circuit peak current. The trip threshold is set to more than 50% of the programmed overload current limit ( I(FASTRIP) = 1.5 x I(LIM)+ 0.375 ). The fast-trip circuit holds the internal FET off for only a few microseconds, after which the device turns back on slowly, allowing the current-limit loop to regulate the output current to I(LIM). Then, device behaves similar to overload condition. Figure 64 through Figure 66 illustrate the behavior of the system when the current exceeds the fast-trip threshold.
9.3.4.3 Start-Up with Short on Output
During start-up into a short circuit current is limited to I(LIM). Figure 67 and Figure 68 illustrate start-up with a short on the output. This feature helps in quick fault isolation and hence ensures stability of the DC bus.
9.3.4.4 Constant Current Limit Behavior During Overcurrent Faults
When power dissipation in the internal FET [PD = (V(IN) - V(OUT)) × I(OUT)] > 10 W, there is a ~0 to 5 % thermal fold back in the current limit value so that I(LIM) drops to IOS. Eventually, the device shuts down due to over temperature.
Figure 46. Fast-Trip Current
9.3.5 FAULT Response
The FLT open-drain output is asserted (active low) during undervoltage, overvoltage, reverse voltage/current and thermal shutdown conditions. The FLT signal remains asserted until the fault condition is removed and the device resumes normal operation. The device is designed to eliminate false fault reporting by using an internal "de-glitch" circuit for undervoltage and overvoltage (2.2-µs typical) conditions without the need for external circuitry. This ensures that fault is not accidentally asserted during transients on input bus.
Connect FLT with a pull up resistor to Input or Output voltage rail. FLT may be left open or tied to ground when not used. V(IN) falling below V(UVF) = 2.1 V resets FLT.
9.3.6 Current Monitoring:
The current source at IMON terminal is configured to be proportional to the current flowing from IN to OUT. This current can be converted to a voltage using a resistor R(IMON) from IMON terminal to GND terminal. This voltage, computed using Equation 6, can be used as a means of monitoring current flow through the system.
The maximum voltage range for monitoring the current (V(IMONmax)) is limited to minimum([V(IN)- 2.2 V], 6.0 V) to ensure linear output. This puts limitation on maximum value of R(IMON) resistor and is determined by Equation 5.
The output voltage at IMON terminal is calculated from Equation 6
Where
- GAIN(IMON) = Gain factor I(IMON):I(OUT) = 52 µA/A
- I(OUT) = Load current
This pin should not have a bypass capacitor to avoid delay in the current monitoring information.
The voltage at IMON pin can be digitized using an ADC (such as ADS1100, SBAS239) to read the current monitor information over an I2C bus.
9.3.7 Power Good Comparator
The device incorporates a Power Good comparator for co-ordination of status to downstream DC-DC converters or system monitoring circuits. The comparator has an internal reference of V(PGTHR) = 0.99 V at negative terminal and positive terminal PGTH can be utilized for monitoring of either input or output of the device. The comparator output PGOOD is an open-drain active high signal, which can be used to indicate the status to downstream units. PGOOD is asserted high when internal FET is fully enhanced and PGTH pin voltage is higher than internal reference V(PGTHR).
The PGOOD signal has deglitch time incorporated to ensure that internal FET is fully enhanced before heavy load is applied by downstream converters. Rising de-glitch delay is determined by Equation 7.
Connect the PGOOD pin with a pull up resistor to Input or Output voltage rail. PGOOD may be left open or tied to ground when not used.
9.3.8 IN, OUT and GND Pins
The device has multiple pins for input (IN) and output (OUT).
All IN pins should be connected together and to the power source. A ceramic bypass capacitor close to the device from IN to GND is recommended to alleviate bus transients. The recommended operating voltage range is 2.7 V – 18 V.
Similarly all OUT pins should be connected together and to the load. V(OUT) in the ON condition, is calculated using the Equation 8
where, RON is the total ON resistance of the internal FET.
GND terminal is the most negative voltage in the circuit and is used as a reference for all voltage reference unless otherwise specified.
9.3.9 Thermal Shutdown:
Internal over temperature shutdown disables turns off the FET when TJ > 160°C (typical). The TPS25940L version latches off the internal FET, whereas TPS25940A commences an auto-retry cycle128 ms after TJ drops below [T(TSD) - 12°C]. During the thermal shutdown, the fault pin FLT pulls low to signal a fault condition.
9.4 Device Functional Modes
9.4.1 DevSleep Mode for SATA® Interface Devices
DevSleep is a new state introduced in the SATA® specification, which requires SATA-based storage solutions to reach a level of low power operation. This is appended to meet the aggressive power/battery life requirements of SATA-based mobile devices. DevSleep enables hosts and devices to completely hibernate the SATA interface. This saves more power versus the existing Partial and Slumber interface power states, which require that the PHY be left powered. In this mode, power consumption is limited to 5 mW or less for SSDs.
Detailed information on DevSleep is available in document 'SATA-DevSleep' and on www.sata-io.org
TPS25940 provides a dedicated DevSleep interface terminal (DEVSLP) to drive the device in low power mode. The DEVSLP terminal is compatible with standard hardware signals asserted from the host controller. When pulled high, it puts the device in low power DevSleep mode. In this mode, the quiescent current consumption of the device is limited to less than 130 µA (95 µA typical). During this mode, the output voltage remains active, the overload current limit is set to I(DEVSLP(LIM)) and functionality of reverse comparator and current monitoring is disabled. All other protections are kept active ensuring the safety of the system even in DevSleep mode.
User must ensure that load currents on the bus are limited to less than I(DEVSLP(LIM)), when the device is driven to DevSleep mode. Also, while coming out of DevSleep, it is important to sequence the TPS25940 earlier than the load. Otherwise, the load can exceed I(DEVSLP(LIM)) and cause TPS25940 to enter the overload mode.
Figure 47 through Figure 50 illustrate the behavior of the system in DevSleep mode.
| V(IN) = 12 V | l(LIM) = 5.3A | |
| C(OUT) = 1 µF | RL = 22Ω |
| RL = 22Ω | l(LIM) = 5.3A | C(OUT) = 1 µF |
| V(IN) = 12 V | l(LIM) = 5.3A | |
| C(OUT) = 1 µF | RL = 15Ω |
| l(LIM–) = 5.3A | C(OUT) = 1 µF | |
9.4.2 Shutdown Control
The internal FET and hence the load current can be remotely switched off by taking the UVLO pin below its 0.6 V threshold with an open collector or open drain device as shown in Figure 51. The device quiescent current is reduced to less than 20 µA in this state. Upon releasing the UVLO pin the device turns on with soft-start cycle.
Figure 51. Shutdown Control