The TPS259461x variants provide an active high digital output (SPLYGD) which is asserted to indicate when the input supply is in a valid range (above UVP/UVLO and below OVLO thresholds) and the device has successfully completed its inrush sequence. This pin can be used as a supply valid status indication to the downstream load or system supervisor.

The SPLYGD pin is an open-drain signal which must be pulled up to an external supply.

After power up, SPLYGD pin is pulled low initially. The device initiates a inrush sequence in which the HFET is turned on in a controlled manner. When the FET gate voltage has reached the full overdrive indicating that the inrush sequence is complete and device is capable of delivering full power, the SPLYGD pin is asserted high. Thereafter, the SPLYGD pin is de-asserted only if the input supply becomes invalid (below UVP/UVLO or above OVLO thresholds). No load side events/faults have any control over the SPLYGD de-assertion.

When there is no supply to the device, the SPLYGD pin is expected to stay low. However, there is no active pulldown in this condition to drive this pin all the way down to 0 V. If the SPLYGD pin is pulled up to an independent supply which is present even if the device is unpowered, there can be a small voltage seen on this pin depending on the pin sink current, which is a function of the pullup supply voltage and resistor. Minimize the sink current to keep this pin voltage low enough not to be detected as a logic HIGH by associated external circuits in this condition.