In the case of a short-circuit and overload current limit when the device interrupts current flow, the input inductance generates a positive voltage spike on the input, and the output inductance generates a negative voltage spike on the output. The peak amplitude of voltage spikes (transients) is dependent on the value of inductance in series to the input or output of the device. Such transients can exceed the absolute maximum ratings of the device if steps are not taken to address the issue. Typical methods for addressing transients include:

• Minimize lead length and inductance into and out of the device.
• Use a large PCB GND plane.
• Connect a Schottky diode from the OUT pin ground to absorb negative spikes.
• Connect a low ESR capacitor larger than 1 μF at the OUT pin very close to the device.
• Use a low-value ceramic capacitor C_IN = 1 μF to absorb the energy and dampen the transients. The capacitor voltage rating must be at least twice the input supply voltage to be able to withstand the positive voltage excursion during inductive ringing.

  Use Equation 19 to estimate the approximate value of input capacitance:

  Equation 19. $\text{V}\text{SPIKE(Absolute) }=\text{V}\text{IN + }\text{I}\text{LOAD}\text{ × }\sqrt{\frac{\text{L}\text{IN}}{\text{C}\text{IN}}}$

  where

  • V_IN is the nominal supply voltage.
  • I_LOAD is the load current.
  • L_IN equals the effective inductance seen looking into the source.
  • C_IN is the capacitance present at the input.
• Some applications can require the addition of a Transient Voltage Suppressor (TVS) to prevent transients from exceeding the absolute maximum ratings of the device. In some cases, even if the maximum amplitude of the transients is below the absolute maximum rating of the device, a TVS can help to absorb the excessive energy dump and prevent it from creating very fast transient voltages on the input supply pin of the IC, which can couple to the internal control circuits and cause unexpected behavior.

Figure 9-10 shows the circuit implementation with optional protection components.

Figure 9-10 Circuit Implementation With Optional Protection Components