ZHCSOF7B september 2022 – june 2023 TPS25990
PRODUCTION DATA
DEVICE_CONFIG is a manufacturer-specific command for configuring or reading several key device setup related information of TPS25990 eFuse.
This command uses the PMBus® read or write word protocol.
The details of this register are shown in Table 9-69.
| Bit | Name | Value | Description | Default | Access |
|---|---|---|---|---|---|
15 | PG_DVDT_DLY | Internal PG delay for discharging DVDT capacitor | Read/Write | ||
1 | 38 ms | 0 | |||
0 | 110 µs | ||||
14 | DIS_VDSFLT | Disable FET drain to source fault detection at start-up | |||
1 | Low drain to source voltage doesn’t trigger a fault | 0 | |||
0 | Low drain to source voltage triggers a fault | ||||
13 | SC_RETRY | Retry after short-circuit fault (Fast-trip) | |||
1 | Retry once into current limit (Not a latched fault) | 0 | |||
0 | Remain off (latched fault) | ||||
12:11 | SPFAIL | Scalable fast-trip threshold | |||
11 | 225% of IOCP(TOTAL) | 10 | |||
10 | 200% of IOCP(TOTAL) | ||||
01 | 175% of IOCP(TOTAL) | ||||
00 | 150% of IOCP(TOTAL) | ||||
10:9 | DVDT_CONFIG | DVDT current scaling | |||
11 | 150% | 10 | |||
10 | 100% | ||||
01 | 75% | ||||
00 | 50% | ||||
8 | VIN_TRAN_DIS | Input transient blanking control | |||
1 | Disabled | 0 | |||
0 | Enabled | ||||
7 | EXT_EEPROM | External EEPROM connection | |||
1 | External EEPROM connected | 0 | Read/Write | ||
0 | External EEPROM not connected | ||||
6 | IREF_DAC2_SEL | IREF/DAC2 pin output selection | Read/Write | ||
1 | DAC2 | 0 | |||
0 | IREF DAC | Read/Write | |||
5 | CMP2_POL | Comparator-2 (COMP2) polarity (AUX pin) | |||
1 | Active Low | 0 | |||
0 | Active High | ||||
4 | CMP1_POL | Comparator-1 (COMP1) polarity (TEMP/CMP pin) | Read/Write | ||
1 | Active Low | 0 | |||
0 | Active High | ||||
3 | ADC_HI_PERF | ADC performance and speed selection | |||
1 | High performance mode (Effective throughput = 18 µs) | 0 | Read/Write | ||
0 | High speed mode (Effective throughput = 11 µs) | ||||
2 | CMP1_IN_SEL | +ve input signal for the Comparator-1 (CMP1) at TEMP/CMP pin | |||
1 | TEMP pin | 0 | |||
0 | IMON pin | Read/Write | |||
1 | CMP1_FLT | Comparator-1 (COMP1) fault (TEMP/CMP pin) | |||
1 | CMP1_FLT is a latched fault and turns off the device | 0 | |||
0 | CMP1_FLT is not a latched fault and doesn’t turn off the device | ||||
0 | CMP2_FLT | Comparator-2 (COMP2) fault (AUX pin) | Read/Write | ||
1 | CMP2_FLT is a latched fault and turns off the device | 0 | |||
0 | CMP2_FLT is not a latched fault and doesn’t turn off the device |
A write command to this register should be preceded by the MFR_WRITE_PROTECT command to unlock the device first to prevent accidental accidental/spurious writes.