VIN_OV_FLT is a standard PMBus® command for configuring or reading a 4-bit threshold for the input overvoltage fault detection. This command uses the PMBus® DIRECT format. When reading and writing to this register, use the coefficients shown in Table 8-67, Equation 19, and Equation 20 to convert between the real world units and hexadecimal values.

This command uses the PMBus® read or write word protocol.

Contents of this register drive a DAC to set the thresholds for a comparator monitoring the input voltage. Once the input voltage exceeds the overvoltage fault rising threshold, the output is turned off, and the VIN_OV_FLT flags are set in the respective registers. The SMBA# signal is asserted. 250 mV (typical) of hysteresis is subtracted from the value in this register. This is to provide the falling threshold the input voltage must fall below for this fault to clear. Once the input voltage falls below the falling threshold, the output is turned back on. However, the fault flags and alerts remain until cleared by the host by sending the CLEAR_FAULTS command.

When an input overvoltage fault is detected, the device:

• sets the FET_OFF and NONE_OF_THE_ABOVE/UNKNOWN bits in the STATUS_BYTE register

• sets the OUT_STATUS, INPUT_STATUS, PGOODB and NONE_OF_THE_ABOVE/UNKNOWN bits in the upper byte of the STATUS_WORD register

• sets the VOUT_UV_WARN bit in the STATUS_OUT register

• sets the VIN_OV_FLT bit in the STATUS_INPUT register

• sets the PGOODB bit in the STATUS_MFR_SPECIFIC_2 register

• notifies the host by asserting SMBA#, if it is not masked setting the STATUS_IN, PGOODB, and STATUS_OUT bits in the ALERT_MASK register and the GPIO4 pin is configured as SMBA# Output in the GPIO_CONFIG_34 register

• deasserts the external PG signal, if the GPIO1 pin is configured as PGOOD output in the GPIO_CONFIG_12 register