Applications which need higher current input protection along with digital interface for telemetry, control, configurability can use one or more TPS25985 devices in parallel with TPS25990 as shown in Figure 9-3.

Figure 9-2 TPS25990 Connected in Parallel with TPS25985x For Higher Current Support With PMBus^®

In this configuration, the TPS25990 acts as the primary device and controls the other TPS25985x devices in the chain which are designated as secondary devices. This configuration is achieved by connecting the primary device as follows:

1. VDD is connected to IN through an R-C filter.

2. DVDT is connected through capacitor to GND.

3. IREF is connected through capacitor to GND.

4. IMON is connected through resistor to GND.

5. ILIM is connected through resistor to GND.

SWEN is pulled up to a 3.3-V to 5-V standby rail. This rail must be powered up independent of the eFuse ON/OFF status.

The secondary devices must be connected in the following manner:

1. VDD is connected to IN through a R-C filter.

2. MODE pin is connected to GND.

3. ITIMER pin is left OPEN.

4. ILIM is connected through resistor to GND.

The following pins of all devices must be connected together:

1. IN

2. OUT

3. EN/UVLO

4. DVDT

5. SWEN

6. PGOOD

7. IMON

8. IREF

9. TEMP

In this configuration, all the devices are powered up and enabled simultaneously.

• The TPS25990 monitors the combined VIN, VOUT, IMON, TEMP and reports it over the PMBus® telemetry interface.

• The OVLO threshold is set to max value in all devices by default. For TPS25985x devices, the OV threshold is fixed in hardware and cannot be changed. The TPS25990 OV threshold can be lowered through PMBus® writes to the VIN_OV_FLT register. In this case, the TPS25990 uses the SWEN pin to turn off the TPS25985x devices during OV conditions.

• The UVLO threshold for all devices is set by the external resistor divider from IN to GND on the EN/UVLO pin. The TPS25990 UV threshold can be changed through PMBus® writes to the VIN_UV_FLT register. In this case, the TPS25990 uses the SWEN pin to turn off the TPS25985x devices during UV conditions.

• During inrush, the output of all the devices are ramped together based on the DVDT capacitor. However, the TPS25990 DVDT sourcing current can be configured through the PMBus® writes to the DEVICE_CONFIG[10:9] register to change the inrush behavior of the whole chain. The TPS25990 controls the DVDT ramp rate for the whole chain and secondary devices simply follow the ramp rate.

• Due to the inherent difference in R_DSON, the current carried by the TPS25990 is lower than the TPS25985x devices. Accordingly, the start-up current limit threshold and active current sharing threshold for the TPS25990 has to be set to a relatively lower value as compared to all the TPS25985x devices by connecting a proportionately higher ILIM resistor.

• The TPS25990 controls the overall overcurrent threshold of the parallel chain by setting the VIREF threshold voltage using its internal DAC. The VIREF voltage can be programmed through PMBus® to change the overcurrent threshold.

• The TPS25990 controls the transient overcurrent blanking interval (t_{OC_TIMER}) for the whole system through PMBus® writes to the OC_TIMER register. Once the digital timer expires, the TPS25990 pulls the SWEN pin low to signal all devices to break the circuit simultaneously.

• The system Power Good (PGOOD) indication is a combination of all the individual device PGOOD indications. All the devices hold their respective PGOOD pins low till their power FET is fully turned on. Once all devices have reached steady-state, they release their respective PGOOD pin pull-down and the PGOOD signal for the whole chain is asserted high. The TPS25985x secondary devices have control over the system PGOOD assertion only during startup. Once in steady state, only the TPS25990 controls the de-assertion of the PGOOD based on the VOUT_PGTH register setting.

• The fault indication (FLT) for the whole system is provided by TPS25990. However, each secondary device also asserts its own FLT independently.

Power up: After power up or enable, all the eFuse devices initially hold their SWEN low till the internal blocks are biased and initialized correctly. After that, each device releases its own SWEN. After all devices have released their SWEN, the combined SWEN goes high and the devices are ready to turn on their respective FETs at the same time.

Inrush: During inrush, because the DVDT pins are tied together to a single DVDT capacitor all the devices turn on the output with the same slew rate (SR). Choose the common DVDT capacitor (C_DVDT) as per Equation 21 and Equation 22.

Refer to Section 8.3.4.1 section for more details.

The internal balancing circuits ensure that the load current is shared among all devices during start-up. This action prevents a situation where some devices turn on faster than others and experience more thermal stress as compared to other devices. This can potentially result in premature or partial shutdown of the parallel chain, or even SOA damage to the devices. The current balancing scheme ensures the inrush capability of the chain scales according to the number of devices connected in parallel, thereby ensuring successful start-up with larger output capacitances or higher loading during start-up. All devices hold their respective PGOOD signals low during start-up. After the output ramps up fully and reaches steady-state, each device releases its own PGOOD pulldown. Because the DVDT pins of all devices are tied together, the internal gate high detection of all devices is synchronized. There can be some threshold or timing mismatches between devices leading to PGOOD assertion in a staggered manner. However, because the PGOOD pins of all devices are tied together, the combined PGOOD signal becomes high only after all devices have released their PGOOD pulldown. This signals the downstream load that it is okay to draw power.

Steady-state: During steady-state, all devices share current nearly equally using the active current sharing mechanism which actively regulates the respective device R_DSON to evenly distribute current across all the devices in the parallel chain. Once PGOOD is asserted, de-assertion is controlled only by TPS25990 and based on VOUT_PGTH register setting.

Overcurrent during steady-state: The circuit-breaker threshold for the parallel chain is based on the total system current rather than the current flowing through individual devices. This is done by connecting the IMON pins of all the devices together to a single resistor (R_IMON) to GND. Similarly, the IREF pins of all devices are tied together and TPS25990 uses internal programmable DAC (VIREF) to generate a common reference for the overcurrent protection block in all the devices. This action helps minimize the contribution of V_IREF variation to the overall mismatch in overcurrent threshold between devices.

In this case, choose the R_IMON as per the following equation:

The start-up current limit and active current sharing threshold for each device is set independently using the ILIM pin. The R_ILIM value for the TPS25990 must be selected based on the following equation:

The R_ILIM value for each TPS25985x must be selected based on the following equation:

Where N = Number of devices in parallel chain (1 × TPS25990 + (N - 1) × TPS25985x)

Other variations: The IREF pin can be driven from an external precision voltage reference with low impedance.

During an overcurrent event, the overcurrent detection of all the devices is triggered simultaneously. This in turn triggers the overcurrent blanking timer (OC_TIMER) in TPS25990. The TPS25990 uses the OC_TIMER expiry event as a trigger to pull the SWEN low for all the devices, thereby initiating the circuit-breaker action for the whole chain at the same time. This mechanism ensures that mismatches in the current distribution, overcurrent thresholds and OC_TIMER intervals among the devices do not degrade the accuracy of the circuit-breaker threshold of the complete parallel chain or the overcurrent blanking interval. However, the secondary devices also maintain their backup overcurrent timer and can trigger the shutdown of the whole chain if the primary device fails to do so within a certain interval.

Severe overcurrent (short circuit): If there is a severe fault at the output (for example, output shorted to ground with a low impedance path), the current builds up rapidly to a high value and triggers the fast-trip response in each device. The devices use two thresholds for fast-trip protection – a user-adjustable threshold (I_SFT = 2 × I_OCP in steady-state or I_SFT = 1.5 × I_LIM during inrush) as well as a fixed threshold (I_FFT only during steady-state). After the fast-trip, the TPS25990 relies on the SC_RETRY configuration bit setting in the DEVICE_CONFIG register to determine if the whole chain enters a latched fault or performs a fast recovery by restarting in current limit manner. If it enters a latched fault, the devices remain latched off till the device is power cycled or re-enabled, or auto-retry after a delay based on the RETRY_CONFIG register setting.