The device monitors V_{(IN_SYS)} and V_(OUT) to provide true reverse current blocking when a reverse condition or input power failure condition is detected. The reverse comparator turns OFF the external blocking FET Q1 quickly as soon as V_{(IN_SYS)} – V_(OUT) falls below –1 V. The total time taken to turn OFF the FET Q1 in this condition is t_{RCB(fast_dly)} + t_(Driver). The delay due to the driver stage t_(Driver) can be calculated using Equation 4.

Equation 4.

where

• RDSON_(Q2) is the on resistance of the fast pull down switch Q2
• Ciss_(Q1) is the input capacitance of the blocking FET Q1
• VGTH_(Q1) is the GATE threshold voltage of the blocking FET Q1
• V_BGATE = 10.2 V (typical)

In a typical system design, t_(Driver) is generally 10% to 20% of t_{RCB(fast_dly)} of 120 nsec (typical).

Figure 9-8 and Figure 9-9 illustrates the behavior of the system during input hot short circuit condition. The blocking FET Q1 is turned ON within 1.6 ms (typical) once the differential forward voltage V_{(IN_SYS)} – V_(OUT) exceeds 67 mV (typical).

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Figure 9-8 Input Hot Short Functionality at 24-V Supply

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Figure 9-9 Input Hot-Short: Fast Trip Response (Zoomed)

The reverse comparator architecture has a supply line noise immunity resulting in a robust performance in noisy environments. This is achieved by controlling the turn OFF time of the internal FET based on the over-drive differential voltage V_{(IN_SYS)} – V_(OUT) over V_(REVTH). Higher the over-drive, faster the turn OFF time, t_RCB(dly).