LDO_1V5 (pin 4), LDO_3V3 (pin 1), and VIN_3V3 (pin 32)

The decoupling capacitors for LDO_3V3, LDO_1V5, and VIN_3V3 (C15, C16, and C17 respectively) need to be placed as close as possible to TPS26750 device for optimal performance. For this example to minimize solution size, the decoupling capacitors are placed on the bottom layer with their ground pads directly underneath the ground pad of TPS26750. Use a maximum of one via per pin from TPS26750 to the decoupling capacitors if placed on a different layer. Use a minimum of 10mil trace width to route these three traces, preferably with 16mil trace width if possible.

CC1 (pin 24) and CC2 (pin 25)

CC1 (C11) and CC2 (C10) capacitors need to be placed as close as possible to their respective pins and on the same layer as the TPS26750 device. When routing the CCx traces, DO NOT via to another layer in between the CCx pins of the TPS26750 to the CCx capacitors. Check to make sure the CCx capacitors are not place outside the CC trace creating an antenna, instead have the traces pass directly through the CCx capacitor pads as shown in the example layout (refer to figure 10-21). Use a minimum of 10mil trace width to ensure Vconn support (5V/0.6A).