ZHCSMM1C April 2023 – February 2024 TPS274C65
PRODUCTION DATA
- 1
- 1 特性
- 2 应用
- 3 说明
- 4 Device Comparison Table
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Pin Diagrams
- 8.3.2 SPI Mode Operation
- 8.3.3 Programmable Current Limit
- 8.3.4 DO_EN Feature
- 8.3.5
Protection Mechanisms
- 8.3.5.1 Overcurrent Protection
- 8.3.5.2 Short Circuit Protection
- 8.3.5.3 Inductive-Load Switching-Off Clamp
- 8.3.5.4 Inductive Load Demagnetization
- 8.3.5.5 Thermal Shutdown
- 8.3.5.6 Undervoltage protection on VS
- 8.3.5.7 Undervoltage Lockout on Low Voltage Supply (VDD_UVLO)
- 8.3.5.8 Power-Up and Power-Down Behavior
- 8.3.5.9 Reverse Current Blocking
- 8.3.6 Diagnostic Mechanisms
- 8.3.7 LED Driver
- 8.4 Device Functional Modes
- 8.5 TPS274C65BS Available Registers List
- 8.6 TPS274C65 Registers
- 9 Application and Implementation
- 10Device and Documentation Support
- 11Revision History
- 12Mechanical, Packaging, and Orderable Information
8.3.1 Pin Diagrams
This section presents the I/O structure of all digital input and output pins.
Figure 8-1 Logic Level Input PinFigure 8-2 shows the input structure for the logic levels pin, CS. The input can be with a voltage or external resistor.
Figure 8-2 Logic Level Input Pin
(CS)Figure 8-3 shows the structure of the open-drain output pin, FAULT. The open-drain output requires an external pullup resistor to function properly.
Figure 8-3 Open Drain Output Pin
(FAULT)