The current limit thresholds and the inrush current time duration can be set by SPI register writes to enable flexible inrush current control behavior. The following table shows the various options available.

An example current limit timing behavior is shown Figure 8-18.

Figure 8-18 Inrush current limit set to 2x ILIM with a delay set by the ILIMDELAY register setting. Initially current load is higher than the twice the limit and then decreases to the 1x limit

The above waveform shows the current limiting behavior on enabling the outputs during the initial inrush period. The initial inrush current period when the current limit is higher enables two different system advantages when driving loads

• Enables higher load current to be supported for a period of time in the order of milliseconds to drive high inrush current loads like incandescent bulb loads.
• Enables fast capacitive load charging. In some situations, it is ideal to charge capacitive loads at a higher current than the DC current to ensure quick supply bring up. This architecture allows a module to quickly charge a capacitive load using the initial higher inrush current limit and then use a lower current limit to reliably protect the module under overload or short circuit conditions.

While in current limiting mode, at any level, the device will have a high power dissipation. If the FET temperature exceeds the over-temperature shutdown threshold, the device will turn off just the channel that is overloaded. After cooling down, the device will either latch off or re-try, depending on the latch configuration. If the device is turning off prematurely on start-up, it is recommended to improve the PCB thermal layout, lower the current limit to lower power dissipation, or decrease the inrush current (capacitive loading).