The TPS274C65xS communicates with the host controller through a high-speed SPI serial interface. The interface has three logic inputs: clock (CLK), chip select (CS), serial data in (SDI), and one data out (SDO). The SDO is three-stated when CS is high. The maximum SPI clock rate is 10 MHz. The capacitance at SPI communication pins (CLK, CS, SDI, SDO) needs to be minimized to achieve high SPI communication frequencies.

The device supports both simple daisy chain1 and addressable SPI; the selection of mode is from the DSPI pin. The main advantage of the addressable SPI mode is that diagnostics and configuration is easier. The two different modes of SPI that is fixed for a given system implementation and cannot be changed dynamically or on the fly. The two modes can be used with or without CRC.

The two modes are described in detail:

1. Addressable SPI mode - non-daisy-chained SPI bus with one single/shared CS through chip addressing. Each chip on the shared SPI is assigned an individual chip address with the address set through a resistor (three-bit address for the chip). Addressed SPI (DSPI pin pulled low) allows direct communication with up to eight TPS274C65xS on a shared SPI using a single shared CS signal. The three-bit address of each IC (up to eight on one board) is set with a resistor to GND on this pin Addressed SPI offers the advantage of direct chip access. CRC check is enabled when CRCEN=1. The SPI main device addresses a specific chip by sending the appropriate A2, A1, A0 logic in the first three bits of the SPI read/write command. The TPS274C65xS monitors the SPI address in each SPI read or write cycle and responds appropriately when the address matches the programmed address for that IC. The added advantage is that it is possible to update the SW state register and read the data in the various read only fault and data registers in every read as well as write command frame. The transmission speed will be faster for addressable SPI compared to the daisy chain SPI as the direct data transmission will happen immediately once the address is transmitted.
2. Daisy chain SPI mode is enabled by setting DSPI pin high. In this mode, multiple TPS274C65xS devices are configured in a serial fashion. In the 16-bit daisy-chain mode, only a minimum read capability and Switch state ON/OFF write is possible- the FAULT status can be read out on each write to the switch ON-OFF register. It is not possible to write to the LED registers or re-configure the device and at the same time update the switch state. However, it is possible to update the SW state register and read the data in the various read only fault and data registers. The 24-bit SPI format allows the write to the SW_STATE register in every read as well as write command frame as well enable CRC. The speed of the transmission for daisy chain will be depending on the CLK frequency as well as the number of devices connected in series.

The communication between the TPS274C65 IC and the controller or MCU is through a SPI bus in a master-slave configuration. The external MCU is always an SPI master that sends command requests on the SDI pin of the TPS274C65 IC and receives device responses on the SDO pin of the IC. The TPS274C65 device is always an SPI slave device that receives command requests and sends responses (such as status and measured values) to the external MCU over the SDO line. The following lists the characteristics of the SPI:

The TPS274C65 device can be connected to the master MCU in the following formats.

• One slave device

Figure 8-4 Independent Slave Configuration

• Multiple slave devices in parallel connection (addressable SPI mode)

Figure 8-5 Addressable SPI Configuration

• Multiple slave devices in series (daisy chain) connection limited only by the SPI write frame speed requirements.

Figure 8-6 Daisy Chain Configuration

SPI mode controls the following functions.

• ON/OFF control of the switches.
• Disable the diagnostics to reduce the quiescent current consumption.
• Select the channel(s) and measurements for VOUT, IOUT and TEMP.
• Fault management (clearing faults and action/response on fault).
• Watchdog timer - the device will generate an error if the SW_STATE register has not been successfully written into within the watchdog timeout period. The customer can disable the watchdog feature using the WD_EN bit (default is off).
• The current limit protection threshold

Note: Please use resistor with <1% tolerance.

SPI Sequence Frame Format

Figure 8-7 24-bit Read, DSPI=0, D24BIT=x, CRC_EN=0

Figure 8-8 24-bit Write, DSPI=0, D24BIT=x, CRC_EN=0

Figure 8-9 32-bit Read, DSPI=0, D24BIT=x, CRC_EN=1

Figure 8-10 32-bit Write, DSPI=0, D24BIT=x, CRC_EN=1

Figure 8-11 16-bit Read, DSPI=1, D24BIT=0, CRC_EN=0

Figure 8-12 16-bit Write, DSPI=1, D24BIT=0, CRC_EN=0

Figure 8-13 24-bit Read, DSPI=1, D24BIT=1, CRC_EN=0

Figure 8-14 24-bit Write, DSPI=1, D24BIT=1, CRC_EN=0

Figure 8-15 24-bit Read, DSPI=1, D24BIT=1, CRC_EN=1

Figure 8-16 24-bit Write, DSPI=1, D24BIT=1, CRC_EN=1