ZHCSMM0 December 2020 TPS27SA08-Q1
PRODUCTION DATA
All timing diagrams assume that the SELx pins are set to 00.
The LATCH, DIA_EN, and EN pins are controlled by the user. The timing diagrams represent a possible use-case.
Figure 9-4 shows the active current limiting behavior of TPS27SA08-Q1 device and the LATCH pin functionality. The switch will not shutdown until either the energy limit or the thermal shutdown is reached.
Figure 9-5 shows the active current limiting behavior of TPS27SA08-Q1 device. The switch will not shutdown until either thermal shutdown or energy limit is tripped. In this example, LATCH is tied to GND and the switch is turned ON when the FET temperature is low enough.
deWhen the switch retries after a shutdown event, the SNS fault indication will remain until VOUT has risen to VBB – 1.8 V. Once VOUT has risen, the SNS fault indication is reset and current sensing is available. ST fault indication is reset as soon as the switch is re-enabled (does not wait for VOUT to rise). If there is a short-to-ground and VOUT is not able to rise, the SNS fault indication will remain indefinitely. The following diagram illustrates auto-retry behavior and provides a zoomed-in view of the fault indication during retry.
Figure 9-6 assumes that tRETRY has expired by the time that TJ reaches the hysteresis threshold.
LATCH = 0 V and DIA_EN = 5 V