ZHCSET0D December 2015 – December 2019 TPS2H000-Q1
PRODUCTION DATA.
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| OPERATING VOLTAGE | ||||||
| VVS(nom) | Nominal operating voltage | 4 | 40 | V | ||
| VVS(uvr) | Undervoltage turnon | VVS rises up | 3.5 | 3.7 | 4 | V |
| VVS(uvf) | Undervoltage shutdown | VVS falls down | 3 | 3.2 | 3.4 | V |
| V(uv,hys) | Undervoltage shutdown, hysteresis | 0.5 | V | |||
| OPERATING CURRENT | ||||||
| I(op) | Nominal operating current(1) | VVS = 13.5 V, VINx = 5 V, VDIAG_EN = 0 V, IOUTx = 0.1 A, current limit = 0.5 A, all channels on | 7 | mA | ||
| I(off) | Standby current | VVS = 13.5 V, VINx = VDIAG_EN = VCS = VCL = VOUTx = THER = 0 V,
TJ = 25°C |
0.5 | µA | ||
| VVS = 13.5 V, VINx = VDIAG_EN = VCS = VCL = VOUTx = THER = 0 V,
TJ = 125°C |
3 | |||||
| I(off,diag) | Standby current with diagnostic enabled | VVS = 13.5 V, VINx = 0 V, VDIAG_EN = 5 V, VVS – VOUTx > V(ol,off), not in open-load mode | 3 | mA | ||
| t(off,diag) | Standby mode deglitch time(1) | IN from high to low, if deglitch time > t(off,deg), the device enters into standby mode. | 10 | 12.5 | 15 | ms |
| Ilkg(out) | Output leakage current in off-state | VVS = 13.5 V, VINx = VOUTx = 0, VDIAG_EN = 5 V | 2 | µA | ||
| POWER STAGE | ||||||
| rDS(on) | On-state resistance(1) | VVS ≥ 3.5 V, TJ = 25°C | 1000 | mΩ | ||
| VVS ≥ 3.5 V, TJ = 150°C | 2000 | |||||
| ICL(int) | Internal current limit | Internal current limit value, CL pin connected to GND | 1 | 1.6 | A | |
| ICL(TSD) | Current limit during thermal shutdown(1) | Internal current limit value under thermal shutdown | 0.8 | A | ||
| External current limit value under thermal shutdown. The percentage of the external current limit setting value | 60% | |||||
| VDS(clamp) | Drain-to-source internal clamp voltage | 46 | 65 | V | ||
| OUTPUT DIODE CHARACTERISTICS | ||||||
| VF | Drain−source diode voltage | IN = 0, IOUTx = −0.15 A. | 0.3 | 0.8 | 1 | V |
| IR(1), IR(2) | Continuous reverse current from source to drain(1) | t < 60 s, VINx = 0 V, TJ = 25°C, single channel reversed, short-to-battery condition | 1 | A | ||
| t < 60 s, VINx = 0 V, GND pin 1-kΩ resistor in parallel with diode. TJ = 25°C. Reverse-polarity condition, all channels reversed | 1 | |||||
| LOGIC INPUT (INx, DIAG_EN, SEL, THER) | ||||||
| VIH | Logic high-level voltage | 2 | V | |||
| VIL | Logic low-level voltage | 0.8 | V | |||
| R(logic,pd) | Logic-pin pulldown resistor | INx, SEL, THER, VINx = VSEL = VTHER = 5 V | 100 | 175 | 250 | kΩ |
| DIAG_EN. VVS = VDIAG_EN = 5 V | 150 | 275 | 400 | |||
| DIAGNOSTICS | ||||||
| Ilkg(GND_loss) | Output leakage current under GND loss condition | 100 | µA | |||
| V(ol,off) | Open-load detection threshold | IN = 0 V, when VVS – VOUTx < V(ol,off), duration longer than t(ol,off), then open load is detected, off state | 1.6 | 2.6 | V | |
| td(ol,off) | Open-load detection threshold deglitch time (see Figure 3) | IN = 0 V, when VVS – VOUTx < V(ol,off) , duration longer than t(ol,off), then open load is detected, off state | 300 | 600 | 800 | µs |
| I(ol,off) | Off-state output sink current | VINx = 0 V, VDIAG_EN = 5 V, VVS = VOUTx = 13.5 V, TJ = 125°C, open load | –75 | µA | ||
| VOL(STx) | Status low-output voltage | ISTx = 2 mA, version A only | 0.2 | V | ||
| VOL(FAULT) | Fault low-output voltage | IFAULT = 2 mA, version B only | 0.2 | V | ||
| tCL(deg) | Deglitch time when current limit occurs(1) | VINx = VDIAG_EN = 5 V, the deglitch time from current limit toggling to FAULT, STx, CS report. | 80 | 180 | µs | |
| T(SD) | Thermal shutdown threshold(1) | 160 | 175 | °C | ||
| T(SD,rst) | Thermal shutdown status reset threshold(1) | 155 | °C | |||
| T(SW) | Thermal swing shutdown threshold(1) | 60 | °C | |||
| T(hys) | Hysteresis for resetting the thermal shutdown or thermal swing(1) | 10 | °C | |||
| CURRENT SENSE (Version B) AND CURRENT LIMIT | ||||||
| K(CS) | Current-sense ratio | 80 | ||||
| K(CL) | Current-limit ratio | 300 | ||||
| VCL(th) | Current limit internal threshold(1) | 0.8 | V | |||
| dK(CS) / K(CS) | Current-sense accuracy, (ICS × K(CS) – IOUTx) /IOUTx × 100 | VVS = 13.5 V, IOUTx ≥ 1 mA | –50% | 50% | ||
| VVS = 13.5 V, IOUTx ≥ 2 mA | –25% | 25% | ||||
| VVS = 13.5 V, IOUTx ≥ 5 mA | –10% | 10% | ||||
| VVS = 13.5 V, IOUTx ≥ 25 mA | –3% | 3% | ||||
| VVS = 13.5 V, IOUTx ≥ 100 mA | –2.5% | 2.5% | ||||
| dK(CL) / K(CL) | External current limit accuracy(2) (IOUTx – ICL × K(CL)) × 100 / (ICL × K(CL)) | VVS = 13.5 V, I(limit) ≥ 50 mA | –25% | 25% | ||
| I(limit) ≥ 100 mA | –20% | 20% | ||||
| I(limit) ≥ 200 mA | –15% | 15% | ||||
| VVS = 13.5 V, 0.5 A ≤ I(limit) ≤ 0.9 A | –10% | 10% | ||||
| VCS(lin) | Current-sense voltage linear range(1) | VVS ≥ 6.5 V | 0 | 4 | V | |
| 5 V ≤ VVS < 6.5 V | 0 | VVS – 2.5 | ||||
| IOUTx(lin) | Output-current linear range(1) | VVS = 13.5 V, VCS(lin) ≤ 4 V | 0 | 0.75 | A | |
| 5 V ≤ VVS < 6.5 V, VCS(lin) ≤ VVS – 2.5 V | 0 | 0.5 | ||||
| VCS(H) | Current sense pin output voltage(1) | VVS ≥ 7 V, fault mode | 4.5 | 6.5 | V | |
| 5 V ≤ VVS < 7 V, fault mode | Min(VVS – 2, 4.5) | 6.5 | V | |||
| ICS(H) | Current-sense pin output current | VCS = 4.5 V, VVS = 13.5 V | 15 | mA | ||
| Ilkg(CS) | Current-sense leakage current in disabled mode | VDIAG_EN = 0 V, TJ = 125ºC | 0.5 | µA | ||