SLVS227G August 1999 – June 2024
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| ttout | Watchdog time out | VDD ≥ VIT– + 0.2V, See timing diagram | 0.8 | 1.4 | 2.1 | s | |
| td | Delay time | VDD > VIT– + 0.2V, See timing diagram | 100 | 180 | 260 | ms | |
| tPHL | Propagation delay time, high-to-low-level output | MR to RESET delay (TPS3123/5/6/8) | VDD ≥ VIT–+ 0.2V, VIL = 0.2 × VDD, VIH = 0.8 × VDD | 0.1 | μs | ||
| tPLH | Propagation delay time, low-to-high-level output | MR to RESET delay (TPS3125/6) | 0.1 | ||||
| tPHL | Propagation delay time, high-to-low-level output | VDD to RESET delay | VIL = VIT– – 0.2V, VIH = VIT– + 0.2V | 10 | μs | ||
| tPLH | Propagation delay time, low-to-high-level output | VDD to RESET delay (TPS3124/5/6) | 10 | ||||