SLVS227G August 1999 – June 2024
PRODUCTION DATA
5 Pin Configuration and Functions
Figure 5-1 TPS3123 / TPS3128: DBV PACKAGE5-Pin SOT-23
Top View
Figure 5-3 TPS3125 / TPS3126: DBV PACKAGE5-Pin SOT-23
Top View
Figure 5-2 TPS3124: DBV PACKAGE5-Pin SOT-23
Top View
Table 5-1 Pin Functions
| PIN | I/O | DESCRIPTION | |||
|---|---|---|---|---|---|
| PIN NUMBER | TPS3123 TPS3128 | TPS3124 | TPS3125 TPS3126 | ||
| 1 | RESET | RESET | RESET | O | Active-Low Output Reset Signal: This pin is driven to a logic low when VDD voltage falls below the negative voltage threshold (VIT-). RESET remains low (asserted) for the delay time period (tD) after VDD voltage rises above VIT+ = VIT- + VHYS. |
| 2 | GND | GND | GND | - | GROUND |
| 3 | MR | - | - | I | Manual Reset: Pull this pin to a logic low to assert a reset signal in the RESET output pin. After MR pin is left floating or pulls to logic high, the RESET output deasserts to the nominal state after the reset delay time (tD) expires. |
| 3 | - | RESET | RESET | O | Active-High Output Reset Signal: This pin is driven to a logic high when VDD voltage falls below the negative voltage threshold (VIT-). RESET remains high (asserted) for the delay time period (tD) after VDD voltage rises above VIT+ = VIT- + VHYS. |
| 4 | WDI | WDI | MR | I | Watchdog Timer Input: If WDI remains high or low longer than the timeout period, then reset is triggered. The timer clears when reset is asserted or when WDI sees a rising edge or a falling edge. |
| 5 | VDD | VDD | VDD | I | Input Supply Voltage: Supply voltage pin. Good analog design practice is to place a 0.1µF ceramic capacitor close to this pin. |