SLVS227G August 1999 – June 2024
PRODUCTION DATA
The TPS312x family of supervisors provide circuit
initialization and timing supervision. Optional configurations include devices with
active-high and active-low output signals (TPS3124/3125/3126), devices with a
watchdog timer (TPS3123/3124/3128), and devices with manual reset
(MR) pins (TPS3123/3125/3126/3128).
RESET output is valid when the supply voltage,
VDD, is above 0.75V. For devices with active-low output logic, the
device monitors VDD and keeps RESET low as long as
VDD remains below the negative threshold voltage, VIT−.
For devices with active-high output logic, RESET remains high as long as
VDD remains below VIT−. An internal timer delays the
return of the output to the inactive state (high) to ensure proper system reset. The
delay time, td, starts after VDD rises above the positive
threshold voltage (VIT− + VHYS). When the supply voltage drops
below
VIT−, the output becomes active (low)
again. All the devices of this family have a fixed-sense threshold voltage,
VIT–, set by an internal voltage divider,
so no external components are required.
The TPS312x family is designed to monitor voltages listed on Table 8-2. For devices with the manual reset functionality, a low level at MR causes RESET to become active. For devices with the watch dog timer functionality, when the supervising system fails to retrigger the watchdog circuit within the time-out interval ttout = 0.8 s, RESET output becomes active for the time period (td). This event also reinitializes the watchdog timer. The devices are available in a 5-pin SOT-23 package and are characterized for operation over a temperature range of −40°C to 85°C.