The Watchdog Window is set via the CWD, SET0, and SET1 pin configurations. To achieve a Watchdog Timeout of 1 second, this design simply leaves CWD pin floating (NC - No Connect) and ties SET0 and SET1 to VDD to set these SET pins to logic high. With this configuration, the Watchdog Lower Boundary t_{WDL (typ)} is set for 800ms and the Watchdog Upper Boundary t_{WDU (typ)} is set for 1.6 seconds. Refer to Table 6.6 Timing Requirements to see the factory-programmed window watchdog timing configurations.

In Figure 8-5 and Figure 8-6 below, the watchdog window timing is shown by causing watchdog faults from pulses on WDI arriving too early and too late, respectively. When a pulse on WDI arrives too early, that is before t_{WDL (min)} or too late, that is after t_{WDU (max)}, a watchdog fault occurs and WDO activates to logic low.

Figure 8-5 Watchdog Fault Caused by WDI Pulse Arriving Too Early (Before t_{WDL (min)})

Figure 8-6 Watchdog Fault Caused by WDI Pulse Arriving Too Late (After t_{WDU (max)})