The watchdog is often needed to be disabled during operation to prevent false watchdog faults. When the watchdog is disabled, all pulses or lack of pulses on WDI are ignored and WDO is high impedance as shown in Figure 8-9. When the watchdog is re-enabled, the watchdog timer is turned back on after a watchdog start-up delay of 150 µs to allow the microcontroller to be monitored by the TPS3431-Q1. To achieve this setup, SET1 on TPS3431 is controlled by a GPIO on the microcontroller and must be logic high to enable to watchdog. To disable the watchdog, the microcontroller sets the GPIO connected to SET1 to logic low. To re-enable the watchdog, the microcontroller sets the GPIO connected to SET1 back to logic high. This configuration is useful when another device or signal is already using the EN pin on TPS3431, and a programmable disable feature with minimal delay upon enable is still required. When the watchdog is disabled using SET1 instead of EN, ENOUT remains unaffected which is useful when needing to disable the watchdog but not causing another device connected to ENOUT to be disabled.