ZHCSO90A november   2022  – april 2023 TPS36-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 器件比较
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Timing Diagrams
    9. 7.9 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Voltage Supervisor
      2. 8.3.2 Window Watchdog Timer
        1. 8.3.2.1 tWC (Close Window) Timer
        2. 8.3.2.2 tWO (Open Window) Timer
        3. 8.3.2.3 Watchdog Enable Disable Operation
        4. 8.3.2.4 tSD Watchdog Start Up Delay
        5. 8.3.2.5 SET Pin Behavior
      3. 8.3.3 Manual RESET
      4. 8.3.4 RESET and WDO Output
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 CRST Delay
        1. 9.1.1.1 Factory-Programmed Reset Delay Timing
        2. 9.1.1.2 Adjustable Capacitor Timing
      2. 9.1.2 Watchdog Window Functionality
        1. 9.1.2.1 Factory-Programmed watchdog Timing
        2. 9.1.2.2 Adjustable Capacitor Timing
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1: Monitoring Microcontroller Supply and Watchdog During Operational and Sleep Modes
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Setting Voltage Threshold
          2. 9.2.1.2.2 Determining Window Timings During Operation and Sleep Modes
          3. 9.2.1.2.3 Meeting the Minimum Reset Delay
          4. 9.2.1.2.4 Setting the Watchdog Window
          5. 9.2.1.2.5 Calculating the RESET Pullup Resistor
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 接收文档更新通知
    2. 10.2 支持资源
    3. 10.3 Trademarks
    4. 10.4 静电放电警告
    5. 10.5 术语表
  12. 11Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Pin Configuration and Functions

GUID-20210630-CA0I-QJPJ-GGTW-VML89JL3BFT0-low.svgFigure 6-1 Pin Configuration Option A
DDF Package, 8-Pin SOT-23,
TPS36-Q1 Top View
GUID-20210630-CA0I-QB3N-JCB7-3CZPPD31LPJX-low.svgFigure 6-3 Pin Configuration Option C
DDF Package, 8-Pin SOT-23,
TPS36-Q1 Top View
GUID-20210630-CA0I-08RM-BC36-BJPP13DHFRN7-low.svgFigure 6-2 Pin Configuration Option B
DDF Package, 8-Pin SOT-23,
TPS36-Q1 Top View
GUID-20210630-CA0I-KCHL-TNFG-6XS1K8BTWC5N-low.svgFigure 6-4 Pin Configuration Option D
DDF Package, 8-Pin SOT-23,
TPS36-Q1 Top View
Table 6-1 Pin Functions
PIN NAME PIN NUMBER I/O DESCRIPTION
PINOUT A PINOUT B PINOUT C PINOUT D
CRST 3 3 — — I Programmable reset timeout pin. Connect a capacitor between this pin and GND to program the reset timeout period. See Section 8.3.4 for more details.
CWD 2 2 — — I Programmable watchdog timeout input. Watchdog close time is set by connecting a capacitor between this pin and ground. See Section 8.3.2.1 for more details.
GND 4 4 4 4 — Ground pin
MR 1 — 2 — I Manual reset pin. A logic low on this pin asserts the RESET. See Section 8.3.3 for more details.
RESET 7 7 7 7 O Reset output. Connect RESET to VDD using a pull up resistance when using open drain output. RESET is asserted when the voltage at the VDD pin goes below the undervoltage threshold (VIT-) or MR pin is driven LOW. For pinout options which do not support independent WDO pin, RESET is also asserted for watchdog error. See Section 8.3.4 for more details.
SET0 5 1 1 1 I Logic input. SET0, SET1, and WD-EN pins select the watchdog window ratios and enable-disable the watchdog; see Section 8.3.2.5 for more details.
SET1 — 5 5 5 I Logic input. SET0, SET1, and WD-EN pins select the watchdog window ratios and enable-disable the watchdog; see Section 8.3.2.5 for more details.
VDD 8 8 8 8 I Supply voltage pin. For noisy systems, connecting a 0.1-µF bypass capacitor is recommended.
WD-EN — — 6 2 I Logic input. Logic high input enables the watchdog monitoring feature. See Section 8.3.2.3 for more details.
WDI 6 6 3 3 I Watchdog input. A falling transition (edge) must occur at this pin during the open window in order for RESET / WDO to not assert. See Section 8.3.2 for more details.
WDO — — — 6 O Watchdog output. Connect WDO to VDD using pull up resistance when using open drain output. WDO asserts when a watchdog error occurs. WDO only asserts when RESET is high. When a watchdog error occurs, WDO asserts for the set RESET timeout delay (tD). When RESET is asserted, WDO is deasserted and watchdog functionality is disabled. See Section 8.3.4 for more details.
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