The manual reset input allows a processor or other logic circuits to initiate a reset. In this section MR is a generic reference to (CTR1 / MR) and (CTR2 / MR). A logic low on MR causes RESET1 to assert on reset output. After MR is left floating, RESET1 will release the reset if the voltage at SENSE1 pin is at nominal voltage. MR should not be driven high, this pin should be left floating or connected to a capacitor to GND, this pin can be left unconnected if is not used.

If the logic driving the MR cannot tri-state (floating and GND) then a logic-level FET should be used as illustrated in Figure 8-8.

Figure 8-8 Manual Reset Implementation

Figure 8-9 Manual Reset Timing Diagram