ZHCSDQ6C April 2015 – March 2024 TPS3702-Q1
PRODUCTION DATA
| PARAMETER | DESIGN REQUIREMENT | DESIGN RESULT |
|---|---|---|
| Monitored rails | 3.3V nominal, with alerts if outside of ±5% of 3.3V (including device accuracy) | Worst case VIT+(OV) = 3.463V
(4.94%), Worst case VIT–(UV) = 3.139V (4.86%) |
| 1.8V nominal, with alerts if outside of ±5% of 1.8V (including device accuracy) | Worst case VIT+(OV) = 1.889V
(4.94%), Worst case VIT–(UV) = 1.712V (4.86%) | |
| 1.2V nominal, with alerts if outside of ±5% of 1.2V (including device accuracy) | Worst case VIT+(OV) = 1.259V
(4.94%), Worst case VIT–(UV) = 1.142V (4.86%) | |
| Output logic voltage | 3.3V CMOS | 3.3V CMOS |
| Maximum device current consumption | 50µA | 40.5µA (maximum), 24µA (typical) |