ZHCSDQ6C April 2015 – March 2024 TPS3702-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 应用
- 3 说明
- 4 Pin Configuration and Functions
- 5 Specifications
- 6 Detailed Description
- 7 Application and Implementation
- 8 Device and Documentation Support
- 9 Revision History
- 10Mechanical, Packaging, and Orderable Information
4 Pin Configuration and Functions
Figure 4-1 DDC PackageSOT-6
Top View
Table 4-1 Pin Functions
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NO. | NAME | ||
| 1 | UV | O | Active-low, open-drain undervoltage output. This pin goes low when the SENSE voltage falls below the internally set undervoltage threshold (VIT–). See the timing diagram in Figure 5-1 for more details. Connect this pin to a pull-up resistor terminated to the desired pull-up voltage. |
| 2 | GND | — | Ground |
| 3 | SENSE | I | Input for the monitored supply voltage rail. When the SENSE voltage goes below the undervoltage threshold, the UV pin is driven low. When the SENSE voltage goes above the overvoltage threshold, the OV pin is driven low. |
| 4 | SET | I | Use this pin to configure the threshold voltages. Refer to Table 8-1 for the desired configuration. |
| 5 | VDD | I | Supply voltage input pin. To
power the device, connect a voltage supply (within the range of 2V
and 18V) to VDD. Good analog design practice is to place a 0.1μF ceramic capacitor close to this pin. |
| 6 | OV | O | Active-low, open-drain overvoltage output. This pin goes low when the SENSE voltage rises above the internally set overvoltage threshold (VIT+). See the timing diagram in Figure 5-1 for more details. Connect this pin to a pull-up resistor terminated to the desired pull-up voltage. |