ZHCSD99A January   2015  – February 2024 TPS3702

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input (SENSE)
      2. 6.3.2 Outputs (UV, OV)
      3. 6.3.3 User-Configurable Accuracy Band (SET)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation (VDD > UVLO)
      2. 6.4.2 Undervoltage Lockout (V(POR) < VDD < UVLO)
      3. 6.4.3 Power-On Reset (VDD < V(POR))
  8. Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Window Voltage Detector Considerations
      2. 7.1.2 Input and Output Configurations
      3. 7.1.3 Immunity to SENSE Pin Voltage Transients
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
  9. Power Supply Recommendations
  10. Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 Evaluation Module
      2. 10.1.2 Device Nomenclature
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 静电放电警告
    6. 10.6 术语表
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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订购信息

Design Requirements

Table 7-1 Design Parameters
PARAMETERDESIGN REQUIREMENTDESIGN RESULT
Monitored rails3.3V nominal, with alerts if outside of ±5% of 3.3V (including device accuracy)Worst case VIT+(OV) = 3.463V (4.94%),
Worst case VIT–(UV) = 3.139V (4.86%)
1.8V nominal, with alerts if outside of ±5% of 1.8V (including device accuracy)Worst case VIT+(OV) = 1.889V (4.94%),
Worst case VIT–(UV) = 1.712V (4.86%)
1.2V nominal, with alerts if outside of ±5% of 1.2V (including device accuracy)Worst case VIT+(OV) = 1.259V (4.94%),
Worst case VIT–(UV) = 1.142V (4.86%)
Output logic voltage3.3V CMOS3.3V CMOS
Maximum device current consumption50µA40.5µA (maximum), 24µA (typical)