The manual reset ( MR) input allows a processor or other logic circuits to initiate a reset. A logic low on MR causes RESET to assert. After MR returns to a logic high and the SENSE pin voltage is within a valid window ((V_IT-(UV) < V_SENSE < V_IT+(OV)) , RESET is deasserted after the reset delay time (t_D). If MR is not controlled externally, then MR can either be connected to V_DD or left floating because the MR pin is internally pulled up to V_DD. Figure Figure 8-2 shows the relation between MR and RESET.

A. RESET pulls up to VDD with 10 kΩ.

B. To initiate and continue time reset counter both conditions must be met MR pin above V_{MR_H} or floating and V_SENSE between V_IT-(UV) + V_HYS and V_IT+(OV) - V_HYS

C. MR is ignored during output RESET low event

Figure 8-2 Manual Reset Timing Diagram