ZHCSIZ9D November 2018 – March 2021 TPS3703-Q1
PRODUCTION DATA
| PARAMETER | DESIGN REQUIREMENT | DESIGN RESULT |
|---|---|---|
| Monitored rails | 3.3-VI/O nominal, with alerts if outside of ±8% of 3.3 V (including device accuracy), 200 ms reset delay | Worst case VIT+(OV) = 3.554 V (7.7%), Worst case VIT–(UV) = 3.046 V (-7.7%) |
| 1.2-VCORE nominal, with alerts if outside of ±5% of 1.2 V (including device accuracy), 10 ms reset delay | Worst case VIT+(OV) = 1.256 V (4.7%), Worst case VIT–(UV) = 1.144 V (-4.7%) | |
| Output logic voltage | 5-V CMOS | 5-V CMOS |
| Maximum system supervision current consumption | 50 µA | 14 µA (7 µA Max each) |