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ZHCSL89B may 2020 – november 2020 TPS3703

PRODUCTION DATA

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机械数据 (封装 | 引脚)

DSE|6
- MPDS287A

散热焊盘机械数据 (封装 | 引脚)

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7.6 Timing Requirements

At 1.7 V ≤ V_DD ≤ 5.5 V, CT = MR = Open, RESET Voltage (V_RESET) = 10 kΩ to V_DD, RESET load = 10 pF, and over the operating free-air temperature range of – 40°C to 125°C, unless otherwise noted. Typical values are at T_J = 25°C, typical conditions at V_DD = 3.3 V.

PARAMETER		TEST CONDITIONS	MIN	NOM	MAX	UNIT
t_D	Reset time delay, TPS3703A, TPS3703E	CT = Open	7	10	13	ms
t_D	Reset time delay, TPS3703A, TPS3703E	CT = 10 kΩ to V_DD	140	200	260	ms
t_D	Reset time delay, TPS3703B, TPS3703F	CT = Open	0.7	1	1.3	ms
t_D	Reset time delay, TPS3703B, TPS3703F	CT = 10 kΩ to V_DD	14	20	26	ms
t_D	Reset time delay, TPS3703C, TPS3703G	CT = Open	3.5	5	6.5	ms
t_D	Reset time delay, TPS3703C, TPS3703G	CT = 10 kΩ to V_DD	70	100	130	ms
t_D	Reset time delay, TPS3703D, TPS3703H	CT = 10 kΩ to V_DD CT = Open		50		µs
t_PD	Propagation detect delay⁽¹⁾ ⁽²⁾			15	30	µs
t_R	Output rise time⁽¹⁾ ⁽³⁾			2.2		µs
t_F	Output fall time⁽¹⁾ ⁽³⁾			0.2		µs
t_SD	Startup delay⁽⁴⁾			300		µs
t_{GI (VIT-)}	Glitch Immunity undervoltage V_IT-(UV), 5% Overdrive⁽¹⁾			3.5		µs
t_{GI (VIT+)}	Glitch Immunity overvoltage V_IT+(OV), 5% Overdrive⁽¹⁾			3.5		µs
t_{GI (MR)}	Glitch Immunity MR pin				25	ns
t_{PD (MR)}	Propagation delay from MR low to assert RESET			500		ns
t_{MR_W}	MR pin pulse width duration to assert RESET		1			µs
t_{D (MR)}	MR reset time delay			t_D		ms

(1) 5% Overdrive from threshold. Overdrive % = [V_SENSE - V_IT] / V_IT; Where V_IT stands for V_IT-(UV)orV_IT+(OV)

(2) t_PD measured from threhold trip point (V_IT-(UV) orV_IT+(OV)) to RESET V_OL voltage

(3) Output transitions from V_OL to 90% for rise times and 90% to V_OL for fall times.

(4) During the power-on sequence, V_DD must be at or above V_{DD (MIN)} for at least t_SD + t_D before the output is in the correct state.