ZHCSNK5B March 2021 – November 2023 TPS3704-Q1
PRODUCTION DATA
| PARAMETER | DESIGN REQUIREMENT | DESIGN RESULT |
|---|---|---|
| Monitored rails | 3.3-V AVDD nominal, with alerts if outside of ±4% of 3.3 V (including device accuracy), 10-ms reset delay | Worst case VIT+(OV) =
3.432 V (+4%) Worst case VIT–(UV) = 3.168 V (–4%) |
| 1.8-V IOVDD nominal, with alerts if outside of ±4% of 1.8 V (including device accuracy), 10-ms reset delay | Worst case VIT+(OV) =
1.872 V (+4%) Worst case VIT–(UV) = 1.728 V (–4%) |
|
| 1.2-V DVDD nominal, with alerts if outside of ±4% of 1.2 V (including device accuracy), 10-ms reset delay | Worst case VIT+(OV) =
1.248 V (+4%) Worst case VIT–(UV) = 1.152 V (–4%) |
|
| SENSE4 (Self-test Option) |
100-kΩ pullup resistor to VDD with NFET pulldown transistor to GND | UV_Trig = High - causing SENSE4 pin
going low UV_Trig = Low - in normal operation |
| Output logic voltage | 5-V CMOS | 5-V CMOS |
| Max system IDD current |
25 µA | 5.5 µA (20 µA maximum) |