ZHCSNK5B March   2021  – November 2023 TPS3704-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Device Nomenclature
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 VDD
      2. 7.3.2 SENSEx Input
        1. 7.3.2.1 Immunity to SENSEx Pins Voltage Transients
          1. 7.3.2.1.1 SENSEx Hysteresis
      3. 7.3.3 RESETx/RESETx
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation (VDD > VDD(MIN))
      2. 7.4.2 Undervoltage Lockout (VPOR < VDD < UVLO)
      3. 7.4.3 Power-On Reset (VDD < VPOR)
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Voltage Threshold Accuracy
      2. 8.1.2 Adjustable Voltage Thresholds
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1: Multi-Rail Window Monitoring for Microcontroller Power Rails
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
      2. 8.2.2 Design 2: Manual Self-Test Option for Enhanced Functional Safety Use Cases
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Guidelines
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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6.5 Electrical Characteristics

At 1.7 V ≤ VDD ≤ 6.0 V, RESETx Voltage (VRESETx) = 10 kΩ to VDD, RESETx load = 10 pF, and over the operating free-air temperature range of – 40°C to 125°C, unless otherwise noted. Typical values are at TA = 25°C, typical conditions at  VDD = 3.3 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD Supply Voltage 1.7 6.0 V
UVLO Under Voltage Lockout (1) VDD falling below 1.7 V 1.2 1.4 1.6 V
UVLO(HYS) UVLO Hysteresis (2) VDD rising below 1.7 V 65 mV
VPOR Power on reset voltage (3) VOL (MAX) = 0.3 V, IOUT = 15 µA 0.7 V
VIT Range Threshold Programming Range 0.4 5.55 V
VIT- (UV) UV accuracy (25℃) 0.1 %
VIT+ (OV) OV accuracy (25℃) 0.1 %
TOL_min Tolerance Programming minimum 3 %
TOL_max Tolerance Programming  maximum 11 %
THR RES Low Threshold Programming Resolution Low VIT ≤ 0.8 V 20 mV / step
THR RES Mid Threshold Programming Resolution Mid 0.8 V < VIT ≤ 4.0 V 0.5 % / step
THR RES High Threshold Programming Resolution High VIT > 4.0 V   20 mV / step
VIT  Accuracy for absolute threshold including tolerance  VIT < 0.8 V  -1.6 1.6 %
VIT  Accuracy for absolute threshold including tolerance  VIT = 0.8 V - 5.55 V   -1 1 %
VHYS VIT < 0.80V 1.1 1.4 1.7 %
VHYS VIT ≥ 0.80V 0.40 0.75 1 %
IDD TPS3704x VDD ≤ 6.0V 5.5 15 µA
ISENSEx Input current, SENSEx pin VSENSEx = 5.5 V 1 2.5 µA
ISENSE_ADJ Input current, SENSE pin (Bypass internal resistor divider)- Adjustible version VSENSEx = 5.5 V 350 nA
VOL Low level output voltage VDD = 1.7 V, ISINK = 0.4 mA 300 mV
VOL Low level output voltage VDD = 2 V, ISINK = 3 mA 300 mV
VOL Low level output voltage VDD = 6.0 V, ISINK = 5 mA 300 mV
I(lkg) Open drain output leakage current VDD = VRESETx = 6.0 V 350 nA
(1) RESETx pin is driven low when VDD falls below UVLO.
(2) Hysteresis is with respect of the tripoint (VIT- (UV), VIT+ (OV)).
(3) VPOR is the minimum VDD voltage level for a controlled output state. Slew rate = 100 mV / µs. 
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