ZHCSS26F november 1998 – october 2020
PRODUCTION DATA
When VDD is greater than 2 V but less than 6 V, the device is within the recommended operating conditions (see Section 7.3). See Table 8-1, Table 8-2, and Table 8-3 for corresponding truth tables.
| MR | VDD > VIT | RESET | TYPICAL DELAY |
|---|---|---|---|
| H → L | 1 | H → L | 30 ns |
| L → H | 1 | L → H | 200 ms |
| H | 1 → 0 | H → L | 3 µs |
| H | 0 → 1 | L → H | 200 ms |
| MR | VDD > VIT | RESET | RESET | TYPICAL DELAY |
|---|---|---|---|---|
| H → L | 1 | H → L | L → H | 30 ns |
| L → H | 1 | L → H | H → L | 200 ms |
| H | 1 → 0 | H → L | L → H | 3 µs |
| H | 0 → 1 | L → H | H → L | 200 ms |
| PFI > VIT | PFO | TYPICAL DELAY |
|---|---|---|
| 0 → 1 | L → H | 0.5 µs |
| 1 → 0 | H → L | 0.5 µs |