In a typical TPS3710-Q1 application, the output is connected to a reset or enable input of the processor (such as a digital signal processor [DSP], central processing unit [CPU], field-programmable gate array [FPGA], or application-specific integrated circuit [ASIC]) or the output is connected to the enable input of a voltage regulator (such as a dc-dc converter or low-dropout regulator [LDO]).

The TPS3710-Q1device provides an open-drain output (OUT). Use a pullup resistor to hold this line high when the output goes to high impedance (not asserted). To connect the output to another device at the correct interface-voltage level, connect a pullup resistor to the proper voltage rail. The TPS3710-Q1 output can be pulled up to 18V, independent of the device supply voltage.

Table 6-1 and the Section 6.3.1 section describe how the output is asserted or deasserted. See Figure 5-1 for a timing diagram that describes the relationship between threshold voltage and the respective output.