ZHCSOP8A March 2022 – September 2023 TPS3760
PRODUCTION DATA
- 1
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Device Comparison
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4 Device Functional Modes
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
7.7 Timing Diagrams
Figure 7-1 Voltage Threshold and
Hysteresis Accuracy
A.
For open-drain output option, the timing diagram assumes the
RESET_UVOD / RESET_UVOD pin is connected via an
external pull-up resistor to VDD.
B. Be
advised that Figure 7-2 shows the
VDD falling slew rate is slow or the VDD decay time is much larger than the
propagation detect delay (tCTR) time.
C. RESET_UVxx / RESET_UVxx is asserted when VDD goes
below the UVLO(MIN) threshold after the time delay, tCTR,
is reached.
Figure 7-2 SENSE Undervoltage (UV) Timing
Diagram
A.
For open-drain output option, the timing diagram assumes the
RESET_OVOD / RESET_OVOD pin is connected via an
external pull-up resistor to VDD.
B. Be
advised that Figure 7-3 shows the
VDD falling slew rate is slow or the VDD decay time is much larger than the
propagation detect delay (tCTR) time.
C. RESET_OVxx / RESET_OVxx is asserted when VDD goes
below the UVLO(MIN) threshold after the time delay, tCTR,
is reached.
Figure 7-3 SENSE Overvoltage (OV) Timing
Diagram